Hu C. – Page 3 – TechConnect Briefs

A Non-Charge-Sheet Analytic Theory for Undoped Symmetric Double-Gate MOSFETs from the Exact Solution of Poissons Equation using SPP Approach

He J., Xi X.i, Chan M., Niknejad A., Hu C., University of California-Berkeley, US

A non-charge-sheet based analytic theory for undoped symmetric double-gate MOSFETs is presented in this paper. The formulation is based on the exact solution of the Poissons equation to solve for electron concentration directly rather than [...]

Quasi-2D Compact Modeling for Double-Gate MOSFET

Chan M., Man T.Y., He J., Xi X., Lin C.H., Lin X., Lin C.H., Lin X., Ko P.K., Niknejad A.M., Hu C., Hong Kong University of Science and Technology, HK

This paper presents an approach to model the characteristics of undoped Double-Gate MOSFETs without relying on the charge-sheet approximation. Due to the extremely thin silicon film used, the inversion charge thickness becomes comparable to the [...]

The Development of Next Generation BSIM for Sub-100nm Mixed-Signal Circuit Simulation

Xi X., He J., Heyderi B., Dunga M., Lin C.H., Heyderi B., Wan H., Chan M., Niknejad A.M., Hu C., University of California at Berkeley, US

This paper describes the next generation BSIM model for aggressively scaled CMOS technology. New features in the model include more accurate non-charge-sheet based physics, completely continuous current and derivatives, and extendibility to non-traditional CMOS based [...]

Modeling of Direct Tunneling Current in Multi-Layer Gate Stacks

Dunga M.V., Xi X., He J., Polishchuk I., Lu Q., Chan M., Niknejad A., Hu C., University of California-Berkeley, US

Device scaling to improve performance calls for reduction of the gate oxide thickness but at a cost of increased direct tunneling gate current. The ITRS 2001 recognizes the need of gate scaling below 2nm and [...]

A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFET’s Operation from the Accumulation to Depletion Region

He J., Xi X., Chan M., Cao K., Niknejad A., Hu C., University of California-Berkeley, US

A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFETs Operation from Strong Accumulation to Depletion region Jin He*+, Xuemei Xi*, Mansun Chan*, and Chenming Hu* (*Electronics Research Laboratory, Department of Electrical Engineering and Computer [...]

Compact Modeling for RF and Microwave Integrated Circuits

Niknejad A.M., Chan M., Hu C., Brodersen B., Xi J., He J., Emami S., Doan C., Cao Y., Su P., Wan H., Dunga M., Lin C.H., University of California at Berkeley, US

Compact modeling has been an integral part of the design of integrated circuits for digital and analog applications. The availability of scalable CMOS device models has enabled rapid simulation and design of present and future [...]

A Framework for Generic Physics Based Double-Gate MOSFET Modeling

Chan M., Taur Y., Lin C.H., He J., Niknejad A., Hu C., Hong Kong University of Science & Technology, HK

This paper presents a framework to develop a generic and physical Double-Gate MOSFET model. Due to limited available physical data and existence of a large variety of device structures, flexibility to assemble model modules to [...]

An Advanced Surface-Potential-Plus MOSFET Model

He J., Xi X., Chan M., Niknejad A., Hu C., University of California at Berkeley, US

Like other surface-potential based model, our surface-potential-plus model starts with charge-sheet approximation, uses the quasi-Fermi-potential to integrate drift and diffusion current and formulates an inversion charge equation that can be analytically solved for given terminal [...]

Present Status and Future Direction of BSIM SOI Model for High-Performance/Low-Power/RF Application

Fung S., Su P., Hu C., IBM Microelectronics, US

The recent progress of BSIM (Berkeley Short-channel IGFET Model) SPICE models extended for SOI transistors are reviewed. The models cover partially depleted (PD), fully depleted (FD) and dynamic depletion (FD) (automatically transition between PD and [...]

Engineering BSIM for the Nano-Technology Era and Beyond

Chan M., Hu C., Hong Kong University of Science and Technology, HK

This paper presents the current status of the forth generation BSIM model and issues of modeling CMOS based devices with nanometer dimensions. Due to the divergence of device structures in sub-0.1 m gate length, it [...]