Dutton R.W. – TechConnect Briefs

Effects of Scaling on Modeling of Analog RF MOS Devices

Liu Y., Cao S., Oh T.Y., Wu B., Tornblad O., Dutton R.W., Stanford University, US

This paper uses advanced TCAD tools—both IMF-based noise modeling and HB-based distortion modeling—to extract parameters of key importance in developing compact models. Additionally, the TCAD-based modeling provides insight into technology constraints that can potentially influence [...]

Implications of Gate Tunneling and Quantum Effects in the Gate-Channel Stack

Dutton R.W., Choi C-H, Stanford University, US

Simulation and modeling of gate tunneling current for thin-oxide MOSFETs and Double-Gate SOIs are discussed. Guidelines for design of leady MOS capacitors are proposed. Resonant gate tunneling current in DG SOI is simulated, based on [...]

Technology Limits and Compact Model for SiGe Scaled FETs

Dutton R.W., Choi C-H, Stanford, US

Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by 2/3 when the [...]

Mobility Extraction and Compact Modeling for FETs Using High-K Gate Materials

Dutton R.W., Liu Y., Choi C-H, Chen T.W., Stanford University, US

This simulation work discusses the impact of direct gate tunneling on effective mobility extraction methods, particularly the Inversion Charge Pumping (ICP) method proposed recently for transistors with high-k gate dielectrics. The valence-band electron gate tunneling [...]

New Capabilities for Verilog-A Implementations of Compact Device Models

Mierzwinski M., OHalloran P., Troyanovsky B., Mayaram K., Dutton R.W., Tiburon Design Automation, US

Acceptance of a model requires its availability in main-stream simulators, yet it can be difficult to get a new model into commercial simulators. In this paper we present simulation results using a compiled Verilog-A architecture [...]

Technology Limits and Compact Model for SiGe Scaled FETs

Dutton R.W., Choi C-H, Stanford, US

Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by 2/3 when the [...]

GEODESIC: A New and Extensible Geometry Tool and Framework with Application to MEMS

Wilson N., Wang K., Yergeau D., Dutton R.W., Stanford University, US

This paper will detail the capabilities of a new geometric modeling tool, called Geodesic, which is being released in source code form to the general community. In addition to providing geometric operations to create geometry [...]

Effects of Surface Properties on the Effective Electrical Gap of Microelectromechanical Devices Operating in Contact

Chan E.K., Dutton R.W., Stanford University, US

The effective electrical gap between two conducting surfaces sandwiching a thin dielectric layer varies with applied voltage and pressure. Improved methods for measuring and modeling this variation are presented. Optical surface profile measurements of fixed-fixed [...]

Investigation of Tetrhedral Automatic Mesh Generation for Finite-Element Simulation of Micro-Electro-Mechanical Switches

Wilson N.M., Pinsky P.M., Dutton R.W., Stanford University, US

Simulation of micro-electro-mechanical systems (MEMS) typically involves the requirement to mesh complex 3-D representations of the geometry. Since proper manual or semi-automated mesh generation requires significant user time and knowledge, there is great interest in [...]

Complete Characterization of Electrostatically-Actuated Beams Including Effects of Multiple Discontinuities and Buckling

Chan E.K., Garikipati K., Dutton R.W., Stanford University, US

The entire process of calibrating an electromechanical simulator ñ identifying relevant parameters, designing and measuring test structures, extracting parameters using detailed electromechanical simulations, and extrapolating the behavior of an actual device ñ is presented. The [...]