Clark W.F. – TechConnect Briefs

Modeling study of capacitance and gate current in strained High–K Metal gate technology: impact of Si/SiO2/HK interfacial layer and band structure model

Garetto D., Rideau D., Dornel E., Clark W.F., Tavernier C., Leblebici Y., Schmid A., Jaouen H., IBM France, FR

The importance of developing predictive modeling tools has considerably increased with the diffusion of nanoscale technologies, in which strained layers and heterojunctions determine the materials modeling complexity. A self--consistent Poisson--Schroedinger solver based on a full-band [...]

Embedded non–volatile memory study with surface potential based model

Garetto D., Zaka A., Quenette V., Rideau D., Dornel E., Clark W.F., Minondo M., Tavernier C., Rafhay Q., Clerc R., Schmid A., Leblebici Y., Jaouen H., STMicroelectronics, FR

Coupling coefficients calculation is known to be a critical issue in Non-Volatile Memory cell compact modelling. To this purpose, the accuracy of the capacitive network method can be significantly improved using the charge balance method, [...]

BSIM Model for MOSFET Flicker Noise Statistics: Technology Scaling, Area, and Bias Dependence

Ertürk M., Anna R., Newton K.M., Xia T., Clark W.F., IBM Systems and Technology Group, US

We have implemented a statistical model for MOSFET flicker noise as an extension to BSIM. Model development methodology and hardware correlation for various types of MOSFETs from 180nm and 130nm technology nodes are presented. Given [...]

Predicting the SOI History Effect Using Compact Models

Na M-H, Watts J.S., Nowak E.J., Williams R.Q., Clark W.F., IBM Corporation, US

A simple and effective compact model methodology that predicts the history effect in silicon-on-insulator (SOI) is discussed. In this study we employ three physical parameters to modify the body-potentials of SOI FETs in an inverter [...]