US – Page 414 – TechConnect Briefs

Unified RLC Model for On-Chip Interconnects

Sim S-P., Yang C., Santa Clara University, US

We present a unified RLC model for deep sub-micron on-chip interconnects. The model consists of two components, a quasi-3D capacitance extraction based on a novel concept of "effective width" and a effective loop inductance model. [...]

A Compact Model Methodology for Device Design Uncertainty

Williams R., Watts J., Na M-H, Bernstein K., Internatoinal Business Machines Corporation, US

Todays ULSI chip and transistor technologies have a high degree of concurrency due to the complexity of new, advanced high performance features. This creates challenges for circuit designer who must account for the evolution of [...]

Double-Gate CMOS Evaluation for 45nm Technology Node

Chiang M-H, An J.X., Krivokapic Z., Yu B., AMD, US

Interest in the double-gate (DG) MOSFET has been growing as transistor development is approaching the end of SIA roadmap. Recent progress in DG technology, and some theoretical study have promoted DG to one of the [...]

Gate Current Partitioning in MOSFET Models for Circuit Simulation

Ngo Q., Navarro D., Mizoguchi T., Hosakawa S., Ueno H., Miura-Mattausch M., Yang C.Y., Santa Clara University, US

Gate current plays a critical role in circuits featuring sub-100nm MOSFETs. This paper elucidates the importance of gate current partitioning for accurate circuit simulation. Past publications have presented gate current models based on surface potential [...]

A Surface-Potential-Based Compact Model of NMOSFET Gate Tunneling Current

Gu X., Wang H., Gildenblat G., Workman G., Veeraraghavan S., Shapira S., Stiles K., Penn State University, US

The continued aggressive scaling of the gate oxide thickness makes the accurate modeling of the gate tunneling current an important aspect of the MOSFET compact model. This work presents a new compact model of which [...]

Application of Genetic Algorithm to Compact Model Parameter Extraction

Cai X., Wang H., Gu X., Gildenblat G., Bendix P., Penn State University, US

The total number of model parameters in compact MOSFET models is usually between 50 and 300, necessitating an elaborate extraction process. Gradient-based optimization techniques were found to be useful but somewhat limited in their scope. [...]

Substrate Current in Surface-Potential-Based Compact MOSFET Models

Gu X., Wang H., Chen T.L., Gildenblat G., Penn State University, US

A new substrate current model was developed which retains the simplicity of the original one but is applicable to all regions of the MOSFET operation with asymtotically correct behaviors and is well suited for use [...]

Modeling of Direct Tunneling Current in Multi-Layer Gate Stacks

Dunga M.V., Xi X., He J., Polishchuk I., Lu Q., Chan M., Niknejad A., Hu C., University of California-Berkeley, US

Device scaling to improve performance calls for reduction of the gate oxide thickness but at a cost of increased direct tunneling gate current. The ITRS 2001 recognizes the need of gate scaling below 2nm and [...]

A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFET’s Operation from the Accumulation to Depletion Region

He J., Xi X., Chan M., Cao K., Niknejad A., Hu C., University of California-Berkeley, US

A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFETs Operation from Strong Accumulation to Depletion region Jin He*+, Xuemei Xi*, Mansun Chan*, and Chenming Hu* (*Electronics Research Laboratory, Department of Electrical Engineering and Computer [...]

Vector Potential Equivalent Circuit for Efficient Modeling of Interconnect Inductance

Pacelli A., SUNY-Stony Brook, US

We present a compact topology for inductive parasitics, using the vector potential as a state variable. The model is local, i.e., only coupling between neighboring wires is explicitly modeled. However, the topology accounts for long-range [...]