Papers – Page 7 – TechConnect Briefs

TopoSim3D/Grain3D: Modeling Surface Deposition and Growth

Gammel J.T., Walker R., Los Alamos National Laboratory, US

We discuss the coupling we are develping between TopoSim3D and Grain3D - two tols making use of the Los Alamos LaGriT adaptive grid toolset. TopoSim3D is a three-dimensional profile simulation tool being developed at Los [...]

Numerical Simulations of Sputter Deposition and Etching in Trenches Using the Level Set Technique

O'Sullivan P.L., Baumann F.H., Gilmer G.H., Bell Laboratories, Lucent Technologies, US

We have performed 2D and quasi-3D numerical simulations of physical vapor deposition (PVD) into high aspect ratio trenches used for modern VLSI interconnects. The topographic evolution is modeled using (continuum) level set methods. The level [...]

An Analytical Field Effect Mobility Model of N- and P-Channel Poly-Si TFTs

Kung J., National Lienho College of Technology and Commerce, TW

An analytical mobility model of the polysilicon (Poly-Si) TFT is important for the design and analysis of display arrays. These transistors can be used both as switching and driving components. Jacunski et al. [1] used [...]

Modelling High Built-In Electric Field Effects on Generation-Recombination Rates in Space-Charge Regions of pn a-Si:H Junctions

Furlan J., Gorup Z., Smole F., Topic M., University of Ljublijana, SI

A theoretical model of lateral transport of charge carriers in pn a-Si:H junctions with high built-in electric fields is proposed in which the transport of carriers is treated in a similar way to capture-emission transitions [...]

Measuring and Characterizing Sub-Micron Short Channel LDD MOSFETs

Liu P.C., Lin H., Nanyang Technological University, SG

An efficient model for accurate predication of the I-V characteristics of submicrometer LDD MOSFET is described in this paper. The model is based on n-th power law model[1] by treating the effective electrical channel length [...]

Self Aligned Gate JFETs for Smart MEMS

Amon S., Vrtacnik D., Resnik D., Krizaj D., Aljancic U., Levstek A., University of Ljubljana, SI

Self Aligned Gate JFET (SJFET) devices and circuits are reported. The problem of electrical isolation between devices on the same chip is realized through Self Aligned Gate approach, enabling the application of standard bipolar discrete [...]

Implementation of Strain Induced Effects in Sensor Device Simulation

Matsuda K., Kanda Y., Naruto University of Education, JP

Device simulation technique is applied to the piezoresistive sensor by including the doping profile and the strain distribution in the silicon substrate. In this simulation, the device equations are solved by Newton's method taking into [...]

Structure Optimization of 140 GHz Pulsed-Mode IMPATT Diode

Zemliak A., Celaya C., Garcia R., Puebla Autonomous University, MX

On the basis of an IMPATT diode complex mathematical model and an optimization procedure, results are presented for a diode structure analysis and optimization suitable for a pulsed-mode 2 mm silicon diode. The complex model [...]

A Predictive Length-Dependent Saturation Current Model Based on Accurate Threshold Voltage Modeling

Lim D., Lim K.Y., Zhou X., Lim D., Lim K.Y., Nanyang Technological University, SG

This paper presents a compact length-dependent saturation current (Idsat) model for deep-submicron MOSFETs based on accurate modeling of the threshold voltabe (Vth). The proposed unified model has considered all the important two-dimensional (2-D) short-channel effects, [...]

Simulation of the Piezo-Tunnel Effect

Friedrich A.P., Besse P.A., Bächtold M., Popovic R.S., Swiss Federal Institute of Technology of Lausanne, CH

We present a new model of the piezo-tunnel effect in a heavily doped silicon p-n junction. Our approach is based on the coupling of a strain-dependent description of the energy exterma in the valence and [...]