Compact Modeling

New Properties and New Challenges in MOS Compact Modeling

Zhou X., See G.H., Zhu G., Zhu Z., Zhu G., Zhu Z., Lin S., Wei C., Srinivas A., Zhang J., Nanyang Technological University, SG

As bulk-MOS technology is approaching its fundamental limit, non-classical devices such as multiple-gate (MG) and silicon-nanowire (SiNW) transistors emerge as promising candidates for future generation device building blocks. This trend poses new challenges in developing [...]

Capacitance modeling of Short-Channel DG and GAA MOSFETs

Børli H., Kolberg S., Fjeldly T.A., Norwegian University of Science and Technology, NO

Based on our framework model of the electrostatics and the drain current in short-channel, nanoscale DG and GAA MOSFETs, we here present a corresponding model for the device capacitances covering all regimes of operation from [...]

Simulation of Buffer-Related Current Slump in AlGaN/GaN HEMTs

Horio K., Shibaura Institute of Technology, JP

Transient simulations of AlGaN/GaN HEMTs are performed in which a three-level compensation model is adopted for a semi-insulating buffer-layer, where a shallow donor, a deep donor and a deep acceptor are considered. Quasi-pulsed I-V curves [...]

Numerical Modeling for Comparison of Emitter-Base Designs of InGaP/GaAs Heterojunction Bipolar Transistors

, Universitat Politecnica de Catalunya, ES

In this work it is investigated the consequences of the design of the emitter pedestal in the electric DC and AC performance of GaInP/GaAs HBTs using numerical modeling TCAD tool. Two different HBTs are studied [...]

A Circuit Compatible Analytical Device Model for Nanowire FET Considering Ballistic and Drift-Diffusion Transport

Paul B.C., Tu R., Fujita S., Okajima M., Lee T., Nishi Y., Toshiba America Research, US

In this paper, we present a simplified circuit compatible analytical device model of nanowire FET for both ballistic and drift-diffusion transport, which can be efficiently used in any conventional circuit simulator like SPICE. The developed [...]

Process Aware Hybrid SPICE Models using TCAD and Silicon Data

Mahotin Y., Tirumala S., Lin X., Pramanik D., Synopsys, Inc., US

This paper describes the methodology for extraction of process dependant hybrid SPICE compact model parameters using calibrated TCAD data and measured Silicon data. Process dependence of electrical curves is, initially, estimated using TCAD data set. [...]

HiSIM- Replacement of BSIM4 in UDSM Circuit Simulations

Iino Y., Pesic I., Silvaco Japan, JP

This paper presents HiSIM speed and convergence advantage against BSIM4 and PSP on a large variety of circuits such as memories, MPUs, PLLs, A/D and D/A converters, mixers etc.

SPICE Modeling of Hook Shaped Idsat Curve for I/O 2.5V MOS Transistors

Tan P.B.Y., Kordesch A.V., Sidek O., Silterra Malaysia Sdn Bhd, MY

In this paper, we demonstrated how we have modified the mobility equation to accurately model the I-V characteristics of I/O 2.5V MOS transistors. Our aim is to model the effect of mechanical STI stress in [...]

A Compact Model for Temperature and Frequency Dependence of Spiral Inductor

Xu Y.Z., Watt J.T., Altera Corporation, US

Spiral inductors fabricated using a 90nm CMOS process have been characterized and analyzed. The extracted series resistance increases with frequency and temperature. The extracted resistance temperature coefficient exhibits a strong dependence on operating frequency. It [...]