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HomeKeywordsprocess simulation

Keywords: process simulation

Computed Metallofullerene Yields in the X@C74 and Z@C82 Series

Slanina Z., Akasaka T., Nagase S., Institute for Molecular Science, JP
A series of metallofullerene formations X@Cn with one common cage Cn and variable encapsulated metals X is treated. The equilibrium composition of the reaction mixture is controlled by the encapsulation equilibrium constants and the saturated [...]

Merging Atomistic and Continuum Simulations of Silicon Technology – The Best from the Two Worlds

Pichler P., Fraunhofer Institute for Integrated Circuits, DE
Simulation of diffusion processes during front-end silicon process stepes needs to address a variety of highly complicated phenomena. In industrial environments, such simulations are nearly entirely based on continuum approaches. The physics entering into the [...]

Practical Atomistic Dopant Diffusion Simulation of Shallow Junction Fabrication Processes and Intrinsic Fluctuations for sub-100nm MOSFETs

Hane M., Ezaki T., Ikezawa T., NEC Corporation, JP
We studied sophisticated shallow junction fabrication processes, i.e. spike-annealing and flash-lamp annealing, using our recently developed atomistic dopant diffusion simulator. Through its use of kinetic Monte Carlo procedure, considering all the possible charged species and [...]

Process and Device Calibration for 31/51nm NMOS/PMOS Devices fabricated by Direct Write E-Beam

Puchner H., Eib N., Kimball J., Mirabedini M., Haywood J., Aronowitz S., Cypress Semiconductor, US
In order to ensure predictability of process and device calibration tools, we manufactured CMOS devices with smallest end-of-line gate electrode dimensions of 31nm and 51nm by applying direct write e-beam lithography. A special test-chip was [...]

Process and Device Calibration for 31/51nm NMOS/PMOS Devices fabricated by Direct Write E-Beam

Puchner H., Eib N., Kimball J., Mirabedini M., Haywood J., Aronowitz S., Cypress Semiconductor, US
In order to ensure predictability of process and device calibration tools, we manufactured CMOS devices with smallest end-of-line gate electrode dimensions of 31nm and 51nm by applying direct write e-beam lithography. A special test-chip was [...]

A 2D Visualization Tool for SUMMiT V Designs

Yarberry V.R., Jorgensen C.R., Sandia National Laboratories, US
This paper describes the 2D Process Visualizer, a CAD tool that enables a SUMMiT (Sandia Ultra-Planar Multilevel MEMS Technology) MEMS designer to visualize the results of applying the process sequence to a mask set by [...]

Modeling of Deposition Process by Level Set Method

Jung H., Kwon O., Yoon S., Won T., Inha University, KR
In this paper, we report a novel method for effectively reducing the amount of calculation for a deposition rate at a specific level-set node. The proposed algorithm makes it possible to reduce the number of [...]

Towards Predictive TCAD and Fab Integration

Fichtner W., Swiss Federal Institute of Technology, CH
This paper gives an overview of the status of technology computer-aided design (TCAD) as it is used today for research, development and manufacturing projects in the micro- and opto-electronics industry. While the accurate and physics-based [...]

Modeling and Simulation of 3D Structures for Gigabit DRAM

Kwon O., Yoon S., Ban Y., Won T., Inha University, KR
In this paper, we present a 3D topography simulator, so-called 3D-SURFILER(SURface proFILER), to model a complicated 3D structure on the substrate for gigabit DRAMs. The 3D-SURFILER comprises a deposition and etching simulator employing a cell [...]

Systematic Global Calibration of a Process Simulator

Lee J-H., Lee S-W., Kim K-D., Kim Y-W., Kong J-T., Lee J-H., Lee S-W., Kim K-D., Kim Y-W., Baek D-H., Samsung Electronics Co.Ltd., KR
This paper proposes a novel methodology of systematic global calibration of a process simulator and validates its accuracy and efficiency with application to memory and logic devices. With 175 SIMS profiles which cover the whole [...]

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