In this paper, we report a novel method for effectively reducing the amount of calculation for a deposition rate at a specific level-set node. The proposed algorithm makes it possible to reduce the number of level-set nodes for the same accuracy and convergence. Furthermore, the total CPU time for simulating the surface evolution on the wafer during the plasma deposition process has been reduced approximately by one-ninth of the required CPU time with comparison to the traditional level-set method. The increased number of level-set nodes with closer grid spacing is generally required for the representation of a curved surface such as a contact hole for multi-level interconnections. However, the CPU time for the level-set calculation of the speed function F increases by O(n2) as we increase the node density by O(n).
Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2001 International Conference on Modeling and Simulation of Microsystems
Published: March 19, 2001
Pages: 422 - 425
Industry sector: Sensors, MEMS, Electronics
Topic: Modeling & Simulation of Microsystems