Xi X. – Page 2 – TechConnect Briefs

The Development of Next Generation BSIM for Sub-100nm Mixed-Signal Circuit Simulation

Xi X., He J., Heyderi B., Dunga M., Lin C.H., Heyderi B., Wan H., Chan M., Niknejad A.M., Hu C., University of California at Berkeley, US

This paper describes the next generation BSIM model for aggressively scaled CMOS technology. New features in the model include more accurate non-charge-sheet based physics, completely continuous current and derivatives, and extendibility to non-traditional CMOS based [...]

Modeling of Direct Tunneling Current in Multi-Layer Gate Stacks

Dunga M.V., Xi X., He J., Polishchuk I., Lu Q., Chan M., Niknejad A., Hu C., University of California-Berkeley, US

Device scaling to improve performance calls for reduction of the gate oxide thickness but at a cost of increased direct tunneling gate current. The ITRS 2001 recognizes the need of gate scaling below 2nm and [...]

A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFET’s Operation from the Accumulation to Depletion Region

He J., Xi X., Chan M., Cao K., Niknejad A., Hu C., University of California-Berkeley, US

A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFETs Operation from Strong Accumulation to Depletion region Jin He*+, Xuemei Xi*, Mansun Chan*, and Chenming Hu* (*Electronics Research Laboratory, Department of Electrical Engineering and Computer [...]

An Advanced Surface-Potential-Plus MOSFET Model

He J., Xi X., Chan M., Niknejad A., Hu C., University of California at Berkeley, US

Like other surface-potential based model, our surface-potential-plus model starts with charge-sheet approximation, uses the quasi-Fermi-potential to integrate drift and diffusion current and formulates an inversion charge equation that can be analytically solved for given terminal [...]