Vasileska D. – Page 4 – TechConnect Briefs

Simulations for Optimized Piezoresistors

Mladenovic D., Vasileska D., Motorola, US

As a phenomenon, piezoresistive effect is well understood from the theoretical point of view. Experimental characterizations have also been done on a variety of uniformly doped samples. However, for modern LSI structures, with shallow diffused [...]

Modeling On-Currents for n-MOSFETs: Ultimate Limits vs. the NTRS

Assad F., Ren Z., Vasileska D., Datta S., Lundstrom M.S., Purdue University, US

The continued evolution of Si technology hinges to a large extent on the ability to maintain high on-currents while achieving low off-currents. As we move from sub-micron to nanoscale technology, it is not at all [...]

An Overview of the 3D Simulation Efforts at Arizona State University Directed Towards Understanding Transport in the Quantum Dots and the Ultra-Small Devices of the Future

Akis R., Vasileska D., Ferry D.K., Arizona State University, US

A brief summary of some of the simulation efforts within the Nanostructure Research Group at Arizona State University is presented, with emphasis on the tools used for modeling deep-submicrometer devices and quantum dot structures under [...]

The Influence of Space Quantization Effect on the Threshold Voltage, Inversion Layer and Total Gate Capacitance in Scaled Si-MOSFETs

Vasileska D., Ferry D.K., Arizona State University, US

We investigate the influence of poly-gate depletion on the inversion layer capacitance CinV, total gate capacitance CtOt and threshold voltage VT in scaled Si MOSFETs using both semiclassical (SC) and quantum-mechanical (QM) description of the [...]