Shangguan W. – TechConnect Briefs

Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach

Chandrasekaran K., Zhu Z.M., Zhou X., Shangguan W., See G.H., Chiah S.B., Rustagi S.C., Singh N., Nanyang Technological University, SG

A compact model for the explicit surface potential equation of doped symmetric double-gate MOSFET from Poisson equation with regional approach is presented. It’s scalable for all doping and channel thicknesses and has been proved to [...]

Scalable MOSFET Short-channel Charge Model in All Regions

See G.H., Chiah S.B., Zhou X., Chandrasekaran K., Shangguan W., Zhu Z., Lim G.H., Pandey S.M., Cheng M., Chu S., Hsia L.-C., NTU, SG

Short-channel effects (SCEs) for both intrinsic chargesand extrinsic capacitances need to be modeled when theMOSFET channel is short. The intrinsic SCEs are modeled using bulk-charge sharing and quasi-two dimensional potential barrier loweirng; extrinsic overlap capacitances [...]

Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling

Zhou X., Chandrasekaran K., Chiah S.B., Shangguan W., Zhu Z., See G.H., Mani Pandey S., Lim G.H., Rustagi S., Cheng M., Chu S., Hsia L.-C., Nanyang Technological University, SG

In this paper, we extend our unified regional approach to bulk-MOS charge modeling with non-pinned surface potential for various device structures such as PD/FD/UTB SOI and s-DG MOSFETs, including strained-Si channel. The regional solutions make [...]

Unified Regional Charge-based MOSFET Model Calibration

See G.H., Chiah S.B., Zhou X., Chandrasekaran K., Shangguan W., Pandey S.M., Cheng M., Chu S., Hsia L.-C., Nanyang Technological University, SG

This paper presents a methodology to extract device physical parameters, i.e., electrical oxide thickness (tox), channel doping (Nch), and poly-gate doping (Ngate), as well as smoothing parameters in our unified regional charge-based model [1] with [...]

One-Iteration Parameter Extraction for Length/width-dependent Threshold Voltage and Unified Drain Current Model

Chiah S.B., Zhou X., Chandrasekaran K., See G.H., Shangguan W., Pandey S.M., Cheng M., Chu S., Hsia L.-C., Nanyang Technological University, SG

This paper presents calibration approach for our unified length/width-dependent MOSFET drain current (Ids) model [1] with the length/width-dependent threshold voltage (Vt) model [2] for technology characterization in the entire geometry/bias range for CMOS shallow trench [...]