McAndrew C. – TechConnect Briefs

BJT Modeling with VBIC, Basics and V1.3 Updates

McAndrew C., Bettinger T., Lemaitre L., Tutt M., Motorola, US

This paper reviews the VBIC BJT model, and details updates in the version 1.3 release. VBICv1.3 includes explicit interaction with siulator global parameters gmin and pnjmaxi, explicit limiting of local temperature rise and exponential arguments [...]

R3, an Accurate JFET and 3-Terminal Diffused Resistor Model

McAndrew C., Motorola, US

This paper presents an improved compact model for diffused resistors and JFETs, valid over geometry, bias, and temperature. The model includes a physically based junction depletion model, a new and accurate velocity saturation model derived [...]

Correlated Noise Modeling and Simulation

McAndrew C., Coram G., Blaum A., Pilloud O., Freescale Semiconductor, US

This paper addresses several issues in noise modeling and simulation. It shows how correlated noise can be implemented in Verilog-A, and presents a new and simple technique to simulate the noise correlation coefficient using only [...]

Advanced Compact Models for MOSFETs

Watts J., McAndrew C., Enz C., Galup-Montoro C., Gildenblat G., Hu C., van Langevelde R., Miura-Mattausch M., Rios R., Sah C-T, Joint Paper, US

The combination of decreasing MOSFET dimensions and increasing use of MOSFETs for analog and RF application has created the need for advanced compact models for MOSFET circuit design. The first generation of MOSFET models rely [...]

R3, an Accurate JFET and 3-Terminal Diffused Resistor Model

McAndrew C., Motorola, US

This paper presents an improved compact model for diffused resistors and JFETs, valid over geometry, bias, and temperature. The model includes a physically based junction depletion model, a new and accurate velocity saturation model derived [...]

Standardization of Compact Device moding in High Level Description Language

Lemaitre L., McAndrew C., Grabinski W., Motorola, CH

This paper proposes a methodology based on hardware description languages (HDL) to efficiently develop compact device models. After an introduction to compact device modeling we describe Verilog-AMS, a popular HDL. Then we show how Verilog-AMS [...]

BJT Modeling with VBIC, Basics and V1.3 Updates

McAndrew C., Bettinger T., Lemaitre L., Tutt M., Motorola, US

This paper reviews the VBIC BJT model, and details updates in the version 1.3 release. VBICv1.3 includes explicit interaction with siulator global parameters gmin and pnjmaxi, explicit limiting of local temperature rise and exponential arguments [...]

Unified Statistical Modeling for Circuit Simulation

McAndrew C., Drennan P.G., Motorola, US

Accurate statistical simulation and modeling are important for IC design. Different types of statistical simulation require different types of statistical models. In this paper a unified approach to statistical modeling and characterization is presented. Based [...]

Numerical Simulation and Analytical Modeling of Strong-Inversion Gate Capacitance in Ultra-Short (30nm) MOSFETs

Sudhama C., Spulber O., McAndrew C., Thoma R., Motorola SPS, US

Bulk and novel MOSFET structures with gate-lengths in the 30nm regime are to become industry standards in ~2007. As devices are scaled down to these lengths, overlap- and fringe-capacitance between the gate and source/drain regions [...]