Papers – Page 5 – TechConnect Briefs

Wafer level integration of epitaxial piezoelectric thin films for novel NEMS, MEMS and MOEMS applications

Dekkers M., Solmates BV, NL

It is well known that Pulsed Laser Deposition (PLD) is a very flexible and versatile technique allowing fast optimization of new and complex material thin films. The unique features of PLD allow for the integration [...]

Spintronics: Recent developments on ultra-low-energy, area-efficient, and fast spin-devices and spin-circuits

Roy K., Purdue University, US

Electronics harnessed by electron's spin-based counterpart, so-called spintronics, has been widely studied in the context of nanomagnets. I will speak on the recent developments on ultra-low-energy, area-efficient, and fast spintronic devices, in particular on electric [...]

CarrICool – the Innovative 3D Interposer Platform for HPC Systems: Analysis, Simulations, Optimization, Practice for Reliability Improvement and Performance Increase

Janczyk G., Bieniek T., Bajurko P., Instytut Technologii Elektronowej, PL

This paper presents specific solutions being developed in frame of the CarrICool (abbr. “Modular Interposer System Architecture providing scalable Heat Removal, Power Delivery and Optical Signaling”) European FP7 project. The presented research and developed solutions [...]

Characteristic Fluctuation of Gate-All-Around Silicon Nanowire MOSFETs Induced by Random Discrete Dopants from Source/Drain Extensions

Sung W-L., National Chiao Tung University, TW

In this study, we explore characteristic fluctuation of gate-all-around silicon nanowire MOSFETs induced by random discrete dopants (RDDs) resulting from source/drain extensions. Compared with the results of source extension, asymmetric variations of characteristics induced by [...]

Simulation of Breakdown Voltage Enhancement in AlGaN/GaN HEMTs with Double Passivation Layers

Horio K., Hanawa H., Shibaura Institute of Technology, JP

It is well known that the introduction of field plate increases the breakdown voltage of AlGaN/GaN HEMTs [1, 2]. However, it increases the parasitic capacitance, leading to the degradation of high-frequency performance. As another way [...]

Positioning of Thermal Via Regions for Reducing Hotspot Temperature in 3D ICs

Maj C., Galicia M., Zajac P., Napieralski A., Lodz University of Technology, PL

The increase of the processor performance is the most desired result of technology evolution. As today’s technology reaches its limits, some other methods has to be developed to uphold performance increase. One of the promising [...]

Effects of Buffer Acceptors on Breakdown Voltages of AlGaN/GaN HEMTs with a High-k Passivation Layer

Kawada Y., Hanawa H., Horio K., Shibaura Institute of Technology, JP

AlGaN/GaN HEMTs are now receiving great interest for application to high-power microwave devices and high-power switching devices. However, the breakdown voltage is known to be greatly lower than that theoretically predicted. To improve the breakdown [...]

Reduction in Lags and Current Collapse in Field-Plate AlGaN/GaN HEMTs with High Acceptor Density in a Buffer Layer

Saito Y., Tsurumaki R., Noda N., Horio K., Shibaura Institute of Technology, JP

We make a two-dimensional transient analysis of field-plate AlGaN/GaN HEMTs with a semi-insulating buffer layer, where a deep acceptor above the midgap is considered. It is studied how the deep-acceptor density and the field plate [...]

Objectification Parallel Computing: A Real-time Solution for Big Data Computing

Li X., Liao W., Yang Z., Liao W., Zhou C.C., NARI Group Corporation, CN

Big data computing is one of the most significant research focuses in the Internet of Things and cloud computing. Hadoop technology in particular has high calculation efficiency in the non-real-time scenario (computing time around 1 [...]

A Neural Network Method to Model Nanoscale FinFET Performance

He J., Peking University Shenzhen SoC Key Lab., CN

This paper presents a neural network method to model nanometer FinFET performance. The principle of this method is firstly introduced and its application in modeling DC and conductance characteristics of nanoscale FinFET transistor is demonstrated [...]