Positioning of Thermal Via Regions for Reducing Hotspot Temperature in 3D ICs

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The increase of the processor performance is the most desired result of technology evolution. As today’s technology reaches its limits, some other methods has to be developed to uphold performance increase. One of the promising method is 3D stacking that should be commonly used in commercial products in near future. However, one of the main challenges is to overcome the thermal problems due to increase of power density. If we take into consideration that present one layer high performance processors tend to overheat, 3D processors will have to be designed in different way to lower junction-to-ambient thermal resistance. A few solution has been proposed to overcome this problem. Nonetheless, the use of thermal vias seems to be one of the most interesting approaches. In general through-silicon vias (TSV) were designed to provide electrical connection between chip layers. However, the material used for its fabrication (copper) has much higher thermal conductivity than silicon. Thus, TSVs significantly improve the heat flow between chip layers resulting in lower maximal temperature in the die. Therefore, this method will be presented in this paper and several floorplans will be investigated in 3D processor in terms of temperature reduction. In our investigation for the location of thermal vias we only considered the regions where TSVs do not significantly disturb the actual floorplan. We take into consideration a 22 nm technology Intel Haswell processor [9], concretely the high performance model i7-5960X. Next, we analyze the hypothetical 3D implementation of this processor in two layers (fig. 1). We compared six floorplans which include thermal via regions placed in various locations. Hotspot thermal modelling tool has been used to compute the temperature distribution in the 3D chip. The input data for Hotspot (power dissipation in each processor block) were obtained with combined Gem5 and McPAT simulators. We evaluated the impact of each case on the maximal temperature and on the thermal gradient. Figure 3 shows the temperature in the processor across the core layer for each floorplan. The results show that via regions placed between the cores significantly reduces the maximal temperature in the die. For base floorplans (V0, V2), the maximal temperature is lower by 6ºC / 7ºC and additionally induces high gradient on edges. Next floorplan (V4) was designed to decrease the gradient. Thus, vias were placed only on top and bottom edges. The temperature drop is now 4ºC but the gradient is almost invisible. Adding vias on other edges of the die (V3) does not reduce the maximal temperature but only induces higher gradient. Finally, the floorplan with vias in all previously used locations (V1) gives the highest temperature drop by 9ºC but with high gradient, similar to V2. In conclusion our investigation shows that thermal vias can reduce the maximal temperature even close to the one of the equivalent 2D structure. Furthermore, it is possible to influence the thermal gradient and to obtain significant peak temperature reduction with no additional gradient. The full paper will present in detail the methodology of simulations and the results.

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Journal: TechConnect Briefs
Volume: 4, Informatics, Electronics and Microsystems: TechConnect Briefs 2017
Published: May 14, 2017
Pages: 35 - 38
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: Informatics, Modeling & Simulation
ISBN: 978-0-9988782-1-8