Nanoelectronics – Page 55 – TechConnect Briefs

First-principle Study for Neutral Indium Migration in Silicon

Yoon K-S, Won T., Inha University, KR

We could figure out the atomistic configurations and migration energy during indium diffusion in silicon through our ab-initio calculations, which consists of searching for saddle points from a minimum and reaction pathway between the two [...]

Revealing of a Particular Physical Mechanism of Disordered Photocatalytic Structure Functioning

Evstratov A., Chis C., Taulemesse J.-M., Gaudon P., Peirano F., Ales Hihg Mining School, FR

Both reduction and oxidation products are simultaneously formed at the surface of the crystalline (“classic”) photocatalysts. As to probable photocatalytic properties of disordered structures, their functioning could be provided by a reinforced artificial separation of [...]

Novel Function of the Boron Icosahedron; a New Mediator of Magnetic Interaction

Mori T., National Institute for Materials Science, JP

Rare earth borides containing the B12 icosahedron display surprisingly strong magnetic interactions although they are magnetically dilute insulating materials with localized f-electrons. A microscopic local probe, ESR, was utilized to investigate the mechanism of the [...]

Active Coatings Technologies for Customized Military Coating Systems

Zunino III J.L., U.S. Army ARDEC, US

The main objective of the U.S. Army’s Active Coatings Technologies Program is to develop technologies that can be used in combination to tailor coatings for utilization on Army Materiel. The Active Coatings Technologies Program, ACT, [...]

Nanoscale Structures and Devices

Nano Scale Autonomous Error-Tolerant (AET) Cellular Network

Liu J., Weerasekera R., Zheng L-R, Tenhunen H., Royal Institute of Technology (KTH), SE

we propose a bottom-up approach using nano-CMOS hybrid Autonomous Error-Tolerant (AET) cellular network architecture. In our approach, each hexagonal AET cell consists of a nano-core dedicated for local computing, CMOS cell peripherals responsible for cell [...]

Fault Tolerant Quantum Computation with new Reversible Gate

Vasudevan D.P., Lala P.K., Parkerson J.P., University of Arkansas, Fayetteville, US

Current CMOS technology will be promising only for the next two decades or less until it reaches its physical limit. Once the atomic level of system design comes to the road of technology, Quantum mechanics [...]

Modules and Circuits

Nano Tungsten Silicide Thin Film Deposition and its Integration with Poly-Silicon

Li M., Suryanarayanan Iyer R., Applied Materials Inc., US

The semiconductor transistor of 90 nm or below generation requires low resistance materials for gate metallization. A thin tungsten silicide (WSix) film is a candidate for the buffer material between poly-silicon and metal, such as [...]

Nanoscale Reaction Analysis of Resist Materials for Nanolithography

Kozawa T., Saeki A., Okamoto K., Tagawa S., Osaka University, JP

Recently, in semiconductor industry, elaborate extension of photolithography is getting closer to its capacity limit and post-optical lithographies have attracted much attention ever. Because they are capable of fabricating features below 32 nm, they are [...]