Modeling & Simulation of Microsystems – Page 77

PSDesigner: A Framework for Transistor Co-Optimization

Burch R., Saxena S., Mozumder P.K., Vasanth K., Davis J., Rao S., Texas Instruments, Inc., US

One challenge for modern CMOS technology is the manufacture of dissimilar transistors on a sin~le chip at minimum cost. For example, hioh performance transistors for critical paths and low power transistors can be combined to [...]

A Universal Low-Field Electron Mobility Model for Semiconductor Device Simulation

Kaiblinger-Grujin G., Selberherr S., Vienna Technical University, AT

We present analytical electron mobility formulae for Si which treat the dependence on all common dopants, such as P, As, Sb, and B in a unified manner. The expressions are derived from Monte Carlo (MC) [...]

Modeling

Three-Dimensional Simulation of Bulge Formation in Contact Hole Metalization

Pyka W., Selberherr S., Technical UniversityVienna, AT

During sputter deposition of metal layers bulges at sharp convex corners can arise and are observed after metalization of contact holes for semiconductor circuits. We present an explanation of this phenomenon by assuming that in [...]

Numerical Simulation for the Sacrificial Release of MEMS Square Diaphragms

Li W.J., Liu J., Shih J.C., Mai J.D., Ho C-M., Liu J., Tai Y-C., UC-Los Angeles, US

Chemical etching of sacrifeial layers is a widely used technique in surface micromachining Etch rate prediction of the sacrif cial layer in an etchant is critical for optimizing a giving fabrication process. This paper presents [...]

Modeling Image Formation in Layered Structures: Application to X-ray Lithography

Bollepalli S.B., Khan M., Cerrina F., UW-Madison, US

In the fabrication of semiconductor devices using lithography, the modeling of the exposure process is very often needed. The elements of a typical exposure system from a modeling perspective comprise of a radiation source, a [...]

A Method of MOSFET Dopant Profile Prediction and its Use in Transistor Design

Kulkarni M., Vasanath K., Davis J., Saxena S., Pollack G., Texas Instruments, Inc., US

As MOS transistor size shrinks to sub-quartermicron dimensions, accurate knowledge of the dopant concentration in various regions of the transistor is becoming more and more important for device simulations. We have developed a methodology to [...]

A Semi-Empirical Resist Dissolution Model for Sub-micron Lithographies

Khan M., Bollepalli S.B., Cerrina F., UW-Madison, US

In this paper, we present a new resist dissolution model suitable for large range of application domains - from memory devices employing < 130nm design rules to MEMS devices with design rules exceeding 10s of [...]

Computer Aided Mask-Layout for Bulk Etch Fabrication

Long M.K, Burdick J.W., Antonsson E.K., California Institute of Technology, US

This paper presents a method to synthesize the mask layout geometry for a MEMS wet etching process. Given a desired part geometry, the method determines a candidate mask geometry that will etch to the final [...]

Molecular Dynamics (MD) Simulations of Reactive Ion Etching (RIE) of Silicon by Cl, Cl2, Br and Br2 Cations

Valone S.M., Hanson D.E., Kress J.D., Los Alamos National Laboratory, US

Simulations of Cl plasma etch of Si surfaces with MD techniques agree reasonably well with the available experimental information on yields and surface morphologies. This information has been supplied to a Monte Carlo etch profile [...]