Keywords: transistor co-optimization
One challenge for modern CMOS technology is the manufacture of dissimilar transistors on a sin~le chip at minimum cost. For example, hioh performance transistors for critical paths and low power transistors can be combined to create a hi~h performance chip with reduced power consumption. One approach is to separately design each transistor and duplicate the lithooraphy steps to allow for separate oate oxide, drain extender, channel, etc. Hc~vever, cost concerns require the minimum number of duplicated lithography steps. We have developed a transistor co-optimization methodology and tool, PSDesigner, that can be used to simultaneously design multiple, coupled transistors to meet disparate goals. PSDesigner facilitates the exploration of the costperformance trade-offs that result from duplicatin~ different lithography steps.
Journal: TechConnect Briefs
Volume: Technical Proceedings of the 1998 International Conference on Modeling and Simulation of Microsystems
Published: April 6, 1998
Pages: 76 - 81
Industry sector: Sensors, MEMS, Electronics
Topics: Informatics, Modeling & Simulation, Modeling & Simulation of Microsystems