Advanced Manufacturing – Page 55

Atomic Holographic Optical Storage Nanotechnology

Thomas M.E., Colossal Storage Corp., US

Colossal Storage Inc. has exclusive license patent rights on new ways of non - contact reading and writing with non destructive reading of information to a ferroelectric molecule. These methods will be used to develop [...]

Miniaturized High Speed Visualization Setup for the Diagnostics of Dynamical Processes in Microsystems

Brugger H., Maier C., Hofer E.P., University of Ulm, DE

For the real time visualization of the dynamics of MEMS it is often inevitable to use high speed camera systems because of the optical enlargement. The micro diagnostic system MinVis, which consists of a miniaturized [...]

Commercial Tools, Processes and Materials

Numerical Analysis of Nano-imprinting Process Based on Continuum Hypothesis

Kim B.S., Kim H-C, Woo Y.S., Lee W.I., Oh S.I., Kim B.S., Kim H-C, School of Mechanical and Aerospace Engineering, Seoul National University., KR

Nano-imprint lithography (NIL) is a processing tech-nique capable of transferring nano-scale patterns onto a thin film of thermoplastics such as polymethyl methacrylate (PMMA). Feature sizes down to 10 nm have been demonstrated to be made [...]

Microscope Slide Electrode Chamber for Nanosecond, Megavolt-Per-Meter Biological Investigations

Sun Y., Vernier P.T., Behrend M., Marcu L., Gundersen M.A., University of Southern California, US

Nanosecond pulsed electric fields pass through the external membranes of biological cells (which have typical response times much greater than nanoseconds) and perturb fast-responding intracellular structures and processes. To enable real-time imaging and investigation of [...]

Inverse RIE Lag of Silicon Deep Etching

Chung C.K., Chiang H.N., National Cheng Kung University, TW

This paper reports for the first time that the phenomena and reaction mechanism of inverse reactive ion etching (RIE) lag occurs in the silicon deep RIE process without feature coalescence. This phenomenon is related to [...]

Process Factors in the Reduction of Output Conductance in Sub-micron CMOS

May N.C., Tan H.S., Kordesch A.V., SILTERRA (M) SDN BHD, MY

CMOS Analog circuits require transistors with low output conductance (gds) in order to achieve high gain. Submicron MOSFETs with halo implants and retrograde wells are designed to have high transconductance (gm) but often suffer from [...]

Planarize the Sidewall Ripples of Silicon Deep Reactive Ion Etching

Weng K-Y, Wang M-Y, Tsai P-H, Industrial Technology Research Institute, TW

In order to diminish the sidewall defects in silicon deep reactive ion etching process, depositing doped silicon dioxide and post-annealing processes are applied. Compared with conventional approaches, the filling-reflow surface shows nearly optical quality. the [...]

Wafer and MEMS Processing

Process for Extremely Thin Silicon-on-Insulator Wafer

Usenko A.Y., Carr W.N., Chen B., Silicon Wafer Technologies, Inc., US

We observe hydrogen platelets buildup into single crystalline silicon caused by hydrogen plasma processing. The platelets are aligned along a layer of lattice defects formed in silicon before plasma processing. The buried defect layer is [...]