Recent Enhancements of MOS Model 11
MOS Model 11 (MM11) is a surface-potential-based compact MOSFET model, which was introduced in 2001 (level 1100). An update of MM11, level 1101, was introduced in 2002. At the moment a second update of MM11, [...]
Sector: Sensors, MEMS, Electronics
Technology Limits and Compact Model for SiGe Scaled FETs
Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by 2/3 when the [...]
An Optimization Method of Deep Submicron SOI Compact Model Parameter Extraction
As SOI rapidly advances to the vanguard of ULSI technology, compact model parameter extraction for SOI still relies on indirect methods. Floating body (FB) device parameter extraction is currently based on body contact (BC) devices. [...]
HiSIM-1.2: The Effective Gate Length Validation with the Capacitance Data
HiSIM-1.2 model parameter extraction and the resulted fit for the current voltage characteristics were reported at WCM-2004 (Boston, MA, 2004). The measurement curves were reproduced well. However, the Cgc (the gate to the shorted source/drain) [...]
Airgap and Line Slope Modeling for Interconnect
We have devised a generic methodology for characterizing airgaps and line slope and including those features in interconnect modeling. The method is silicon-based and can be used to accurately model the impact on capacitance. Our [...]
Modeling Snapback and Rise-time Effects in TLP Testing for ESD MOS Devices using BSIM3 and VBIC Models
A simple SPICE macro model has been created for ESD MOS modeling. The model consists of standard components only. It includes a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a [...]
How To Design for Analog Yield using Monte Carlo Mismatch SPICE Models
The downscaling of devices causes the unpredictability of analog circuit yield. Transistor mismatch is one of the obstacles to achieving high yield. Analog circuit designers usually run Monte Carlo mismatch models to predict the functionality [...]