Borse H.S., Jawake A.V., Aher S.R., Bhosale K.S., Patil G.C., Patil S.R., Patil G.C., Patil S.R., Bormane D.S.
JSPM’s Rajarshi Shahu College of Engineering, IN
Keywords: DIBL, junctionless transistor, sub-threshold slope, unity gain frequency
Junctionless transistor (JLT) attracts the researchers due to its advantages over conventional MOSFET’s namely high scalability, simple process flow, and low thermal budget. However, scaling of JLT below 20 nm regime results increase in off state leakage, variation threshold voltage (VT) and dominant short channel effects (SCE). Reducing gate oxide thickness improves the channel control. However, it increases the gate leakage current. In this paper comparative study on intrinsic performance parameters of Bulk planer junctionless transistor with high-k gate oxide has been carried out by using two dimensional Cogenda Visual TCAD simulator. The process parameters consider here are gate length and gate oxide materials (SiO2, Si3N4, and HfO2). The impact gate oxide materials on electrical parameters namely ON state current (ION), Sub-threshold slope (SS) and drain induce barrier lowering (DIBL) in addition with analog performance parameters, namely transconductance (gm), unity gain frequency (FT), and gate capacitance (Cgg) has been analyze. For fair comparison threshold voltages (V¬T) of all structures have tuned to 0.25 V, it has been found that impact of high-k dielectric material is more significance when gate length below 20nm.
Journal: TechConnect Briefs
Volume: 4, Advanced Manufacturing, Electronics and Microsystems: TechConnect Briefs 2015
Published: June 14, 2015
Pages: 222 - 225
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: Nanoelectronics
ISBN: 978-1-4987-4730-1