SOI – Page 4 – TechConnect Briefs

Molecular Control of the Drain Current in a Buried Channel MOSFET

Yang J., de la Garza L., Thornton T.J., Kozicki M., Gust D., Arizona State University, US

We present results from a buried channel MOSFET with a molecular monolayer deposited on the surface. After attachment of the monolayer, the threshold voltage of the device shifts by approximately – 4.5 V. We explain [...]

Measurements and Modeling of Mobility in Ultra-Thin SOI

Mastrapasqua M., Esseni D., Fiegna C., Agere Systems, US

We present a study of the effective mobility (ueff) of ultra thin SOI n MOSFETs for both single and double gate operation. Electron mobility was measured for silicon thickness Tsi down to approximately 5 nm [...]

How to Build an SOI MOSFET Compact Model without Violating the Laws of Physics

Watts J., IBM Microelectronics, US

An important application for partially depleted SOI is high performance microprocessors and other logic chips. In order to deliver market leading performance it is necessary for transistor design and circuit design to be done concurrently. [...]

Present Status and Future Direction of BSIM SOI Model for High-Performance/Low-Power/RF Application

Fung S., Su P., Hu C., IBM Microelectronics, US

The recent progress of BSIM (Berkeley Short-channel IGFET Model) SPICE models extended for SOI transistors are reviewed. The models cover partially depleted (PD), fully depleted (FD) and dynamic depletion (FD) (automatically transition between PD and [...]

A New Lateral Trench Sidewall Schottky (LTSS) Rectifier on SOI

Singh Y., Kumar M.J., Indian Institute of Technology, IN

In this paper, a new Schottky rectifier structure, called Lateral Trench Sidewall Schottky (LTSS) rectifier on SOI is presented. Based on two-dimensional simulations, we demonstrate that the proposed device is superior in performance as compared [...]