gate-all-around (GAA) – TechConnect Briefs

An Analytic Potential Based Model for Gate-All-Around Nanowire Tunnel-FETs

Liu Y., He J., Chan M., Peking University Shenzhen SOC Key Laboratory, CN

In this paper, an analytic potential based current model of the gate-all-around (GAA) silicon nanowire tunnel-FETs (NW-TFETs) is proposed based on the surface potential solutions at the channel direction and considering band to band tunneling [...]

Performance Comparison of Non-planar MOSFETs

Liao Y.-B., Chiang M-H, Hsu W.-C., National Ilan University, TW

To gain insights into device variability, device scalability and even circuit performance, more comprehensive simulation data are presented. FinFET shows the highest transconductances corresponding to aforementioned highest IDLIN and IDSAT. Regarding process variation, same W¬Si/D [...]

Xsim: A Unified Compact Model for Bulk/SOI/DG/GAA MOSFETs

Zhou X., Nanyang Technological University, SG

This paper presents a unified compact model (Xsim) for bulk/SOI MOSFETs, double-gate (DG) FinFETs, and gate-all-around (GAA) silicon-nanowires (SiNWs) that has been under development over the past 13 years. One key feature of the model [...]

Variability Study for Silicon Nanowire FETs

Liao Y.-B., Chiang M-H, Kim K., Hsu W.-C., National Cheng Kung University, TW

3-D numerical simulation shows that both the conventional and JL nanowire FETs are sensitive to structural variation whereas the former is more tolerable. Due to more increased Ion/Ioff for lower D and WSi in JL, [...]

Xsim: Benchmark Tests for the Unified DG/GAA MOSFET Compact Model

Zhou X., Zhu G.J., Srikanth M.K., Lin S-H, Chen Z.H., Zhang J.B., Wei C.Q., Yan Y.F., Selvakumar R., Nanyang Technological University, SG

This paper presents benchmark tests of the unified compact model (Xsim) for double-gate (DG) and gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs, which has been developed over the years with the unified regional modeling (URM) approach. The [...]