ESD – TechConnect Briefs

Modeling of High Voltage Devices for ESD Event Simulation

Zhou Y., Salcedo J., Hajjar J.-J., Analog Devices, Inc., US

BCDMOS process technologies are key in enabling highly integrated mixed-signal application for the automotive, medical and industrial sectors. Achieving satisfactory ESD performance in high voltage mixed-signal applications requires synthesized co-design using circuit-level ESD event simulation [...]

Novel Metal Nanowire/Polymer Nanocomposites for Electromagnetic Interference Shielding

Gelves G.A., Al-Saleh M.H., Sundararaj U., University of Alberta, CA

Novel Polymer Nanocomposites containing high aspect ratio metal nanowires with outstanding potential for Electromagnetic Interference applications will be introduced in this presentation. The development and characterization of these novel materials will be presented. Processing-structure-property relationships [...]

Non traditional dicing of MEMS devices

Sullivan S., Yoshikawa T., DISCO Corp., JP

Dicing of MEMS contains a host of challenges. Contamination, vibration, thermal, and electrical sensitivity dictate modified or non traditional dicing processes. Focusing a laser beam inside of the silicon substrate creating a modified layer is [...]

Technology Limits and Compact Model for SiGe Scaled FETs

Dutton R.W., Choi C-H, Stanford, US

Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by 2/3 when the [...]

Modeling Snapback and Rise-time Effects in TLP Testing for ESD MOS Devices using BSIM3 and VBIC Models

Zhou Y., Connerney D., Carroll R., Luk T., Fairchild Semiconductor, US

A simple SPICE macro model has been created for ESD MOS modeling. The model consists of standard components only. It includes a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a [...]

A Unified Compact Model for Electrostatic Discharge Protection Device Simulation

Chou H-M, Cho Y-Y, Chou H-M, Lee J.W., Li Y., National Chiao Tung University, TW

In modern microelectronics manufacturing, whole chip electrostatic discharge (ESD) protection circuit design is necessary for obtaining robust electrical performance [1-5]. In designing the whole chip ESD protection circuit, owing to its high circuit complexity, an [...]

Investigation of Robust Fully-Silicided NMOSFETs for Sub-100 nm ESD Protection Circuits Design

Lee J.W., Tang H., Li Y., Natl Nano Device Labs & Natl Chiao Tung Univ, TW

Electrostatic discharge (ESD) becomes an important issue in vary large scaled integrated (VLSI) circuit design and manufacture, especially for the ultra-thin oxide nano-devices [1-3]. It results from a fact that the gate oxide will be [...]

Technology Limits and Compact Model for SiGe Scaled FETs

Dutton R.W., Choi C-H, Stanford, US

Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by 2/3 when the [...]

Gate Length Scaling Effects in ESD Protection Ultra-thin Body SOI Devices

Lee J.W., Li Y., Sze S.M., Natl Nano Device Labs & Natl Chiao Tung Univ, TW

In this paper we experimentaly explore the gate length scaling effects which related to the abrupt degation of electrostatic discharge (ESD) robustness for ultra-thin body silicon on insulator (SOI) devices and integrated circuits (ICs). It [...]

Compact Modeling of Tunneling Breakdown in PN Junctions for Computer-Aided ESD Design (CAD for ESD)

Subramanian Y., Darling R.B., University of Washington, US

This paper presents compact, physically-based electrothermal models for direct as well as indirect bandgap tunneling processes in pn-junctions for use in network simulators (e.g. Saber or VHDL-A). The model for indirect tunneling has been validated [...]