Investigation of Robust Fully-Silicided NMOSFETs for Sub-100 nm ESD Protection Circuits Design

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Electrostatic discharge (ESD) becomes an important issue in vary large scaled integrated (VLSI) circuit design and manufacture, especially for the ultra-thin oxide nano-devices [1-3]. It results from a fact that the gate oxide will be easily damaged during ESD stressing for their relatively high turn-on voltage of parasitic bipolar junction transistors. In this paper, new fully-silicided NMOSFETs are designed, fabricated, and studied; our investigation demonstrates that this new approach significantly improves sustaining ESD robustness which is than that of the conventional fully-silicided device. Furthermore, it has an excellent electrical efficiency than those of drain ballast resistor tied devices. We conclude that the proposed fully-silicided NMOSFET is very attractive to sub-100nm ESD protection VLSI circuit as well as system-on-chip (SOC) design.

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Journal: TechConnect Briefs
Volume: 3, Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, Volume 3
Published: March 7, 2004
Pages: 194 - 197
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topics: Nanoelectronics
ISBN: 0-9728422-9-2