DRAM – TechConnect Briefs

A Novel Approach of Sample Preparation for SCM Inspection in the DRAM Device Structures

Lue J.L., Liu H.W, Wu E., Pai B., Fan S., Wang T., ProMOS Technologies Inc, TW

This paper discusses the removal of the doped-polysilicon of a gate transistor by wet chemical etching containing the spacer oxide and nitride that remain. This technique significantly improves the image quality of 2-D doping profile [...]

The Design of a Silicon Wire DRAM Cell for Very Dense DRAM Architectures

Bindal A., Aflatooni K., San Jose State University, US

In this study, we propose a new DRAM cell that uses a silicon-wire pass transistor stacked on top of a high-dielectric capacitor rated of holding industry-standard 32 fCoulomb charge. We show that the performance of [...]

Modeling and Simulation of 3D Structures for Gigabit DRAM

Kwon O., Yoon S., Ban Y., Won T., Inha University, KR

In this paper, we present a 3D topography simulator, so-called 3D-SURFILER(SURface proFILER), to model a complicated 3D structure on the substrate for gigabit DRAMs. The 3D-SURFILER comprises a deposition and etching simulator employing a cell [...]

A Methodology for Modeling a Complex Geometry on Wafer from a Layout Data

Yoon S., Kwon O., Won T., Inha University, KR

This paper reports a novel methodology and its application to the modeling of a complex 3D geometry on wafer from a layout data. Our modeling method comprises the steps of: drawing a mask layout; transforming [...]

Influence of Element Size on the Precision and Required Computational Effort for 3D FEM Interconnect Capacitance Simulations of ULSI DRAM Cells

Hieke A., Infineon Technologies Corporation, US

A fundamental proble of all FEM capacitance computations in MEMS and ULSI is to determine proper mesh size for the elements representing the considered model. In particular, opticaml mesh size selection is crucial for large [...]

The 2.4F2 Memory Cell Technology with Stacked-Surrounding Gate Transistor (S-SGT) DRAM

Suzuki M., Endoh T., Sakuraba H., Masuoka F., Tohoku University, JP

This paper reports that the Stacked-Surrounding Gate Transistor (S-SGT) DRAM achieves a cell size of 2.4F 2. The S-SGT DRAM is structured by stacking several SGT-type cells in series vertically. In order to realize cell [...]