This paper reports that the Stacked-Surrounding Gate Transistor (S-SGT) DRAM achieves a cell size of 2.4F 2. The S-SGT DRAM is structured by stacking several SGT-type cells in series vertically. In order to realize cell size of 2.4F 2, we propose the cell design of S-SGT DRAM. By using proposed design, we demonstrate that the S-SGT DRAM can realize cell size of 2.4F 2 by process simulation, while cell size of conventional SGT DRAM is 4.8F 2. Therefore, the S-SGT DRAM is a promising candidate for future ultra high density DRAMs.
Journal: TechConnect Briefs
Volume: Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems
Published: March 27, 2000
Pages: 388 - 391
Industry sector: Sensors, MEMS, Electronics
Topic: Modeling & Simulation of Microsystems