drain current – TechConnect Briefs

A turn‐on DC surface‐potential‐based drain current model for fully‐depleted poly‐Si thin film transistors

Zhu Z., Chu J., Suzhou Vocational University, CN

A turn‐on DC surface‐potential‐based drain current model for fully‐depleted polycrystalline silicon thin film transistors is developed based on the charge sheet model considering both deep and tail acceptor trap states in the grain boundary and [...]

Drain Current Model for Thin Body Undoped and Lightly Doped Double-Gate MOSFETs

Abd Elhamid H., Ineguez B., Ismail Y., Deen MJ., Zewail City of Science and Technology, EG

We developed new compact models that include the QM effects on electrical properties such as the surface potential, and drain current. The models were used to study the impact of subband engineering and holes/electrons IMREF [...]

Discreteness and Distribution of Drain Currents in FinFETs

Lu N., IBM, US

It is likely that the characterization and modeling of a finFET will be carried out on a multi-fin structure, since it is a single electrical device functionally. Discreteness of multiple fins in a multi-fin FET [...]

Unified Modeling of Multigate MOSFETs Based on Isomorphic Modeling Principles

Fjeldly T.A., Monga U., Norwegian University of Science and Technology, NO

A compact, unified and analytical model is presented for the 3D electrostatics of nanoscale, multigate MOSFETs. The model is based on solutions of the 3D Laplace equation (subthreshold) and Poisson’s equation (above threshold), where suitable [...]

Compact Subthreshold Modeling of Rectangular Gate and Trigate MOSFETs

Fjeldly T.A., Monga U., Norwegian University of Technology, NO

We have previously shown that the subthreshold potential distribution of DG and circular gate MOSFETs can be precisely modeled using conformal mapping techniques. Simpler, unified models suitable for circuit design can also be established for [...]

A Unified View of Drain Current Models for Undoped Double-Gate SOI MOSFETs

Ortiz-Conde A., García-Sánchez F.J., Simón Bolívar University, VE

In this paper we discuss the compact modeling framework for undoped double-gate SOI MOSFETs. Core compact models, including the analysis for surface potential and drain current for various device structures are discussed and compared. Then, [...]

One-Iteration Parameter Extraction for Length/width-dependent Threshold Voltage and Unified Drain Current Model

Chiah S.B., Zhou X., Chandrasekaran K., See G.H., Shangguan W., Pandey S.M., Cheng M., Chu S., Hsia L.-C., Nanyang Technological University, SG

This paper presents calibration approach for our unified length/width-dependent MOSFET drain current (Ids) model [1] with the length/width-dependent threshold voltage (Vt) model [2] for technology characterization in the entire geometry/bias range for CMOS shallow trench [...]