Yu B. – TechConnect Briefs

Analytic Charge Model for Double-Gate and Surrounding-Gate MOSFETs

Yu B., Lu H., Lu W-Y, Lu H., Lu W-Y, Taur Y., UCSD, US

An analytic charge model for both double-gate (DG) and surrounding-gate (SG) MOSFETs is presented. With only the mobile charge term, Poisson’s equation is rigorous solved and the analytic electrostatic potential is derived. The development of [...]

One-dimensional Phase-Change Nanowires for Information Storage Application

Sun X.H., Yu B., NASA Ames Research Center, US

The electrically operated phase-change random access memory (PRAM) features faster write/read, improved endurance, and much simpler fabrication as compared with the traditional transistor-based nonvolatile semiconductor memories. Low-dimensional phase-change materials in nanoscale dimensions offer advantages over [...]

Single-Crystal Nanowire Transistor for Logic and Memory Applications

Yu B., Ye L., Meyyappan M., NASA Ames Research Center, US

In this paper we report chemical synthesis, device fabrication, and device physics investigation of 1-D single-crystalline nanowire field-effect transistor (SNW-FET) for logic and memory applications. Wafer-scale transistor arrays were fabricated with semiconducting nanowires serve as [...]

Double-Gate CMOS Evaluation for 45nm Technology Node

Chiang M-H, An J.X., Krivokapic Z., Yu B., AMD, US

Interest in the double-gate (DG) MOSFET has been growing as transistor development is approaching the end of SIA roadmap. Recent progress in DG technology, and some theoretical study have promoted DG to one of the [...]