Wong H.S.P. – TechConnect Briefs

Contact Properties of Titanium Nitride Sidewall Coating for Nanoelectromechanical Electronics

Shavezipur M., Harrison K.L., Lee W-S., Espinosa B., Provine J., Mitra S., Wong H.S.P., Howe R.T., The Ohio State University, US

The performance of hybrid NEM-CMOS low power electronics and logic gates highly depends on the source-drain contact resistance and adhesion force, which affect the power consumption and the pull-in/pull-out hysteresis, respectively. In the present work, [...]

On the Variability of HfOx RRAM: From Numerical Simulation to Compact Modeling

Guan X., Yu S., Wong H.S.P., Stanford University, US

The trap-assisted conduction and filamentary switching mechanisms of the HfOx based resistive memory are studied. A numerical simulator is developed to reproduce the experimental I-V curves. Comparison with experiments shows that the cycle-to-cycle variation in [...]

A Fully Anlytical Model for Carbon Nanotube FETs including Quantum Capacitances and Electrostatics

Wei L., Frank D.J., Chang L., Wong H.S.P., Massachusetts Institute of Technology, US

In this paper, an analytical model of intrinsic carbon nanotube field effect transistors (CNFETs) is presented based on ballistic transport and careful analysis of the quantum capacitances, which requires neither iteration nor numeric integration. Essential [...]

Effective Drive Current in CMOS Inverters for Sub-45nm Technologies

Hu J., Park J-E, Freeman G., Wong H.S.P., Stanford University, US

We propose a new model for the effective drive current (Ieff) of CMOS inverters, where the maximum FET current obtained during inverter switching (Ipeak) is a key parameter. Ieff is commonly defined as the average [...]