Vasileska D. – Page 2 – TechConnect Briefs

Mobility of Electrons in Rectangular Si Nanowires

Ramayya E., Vasileska D., Goodnick S.M., Knezevic I., Arizona State University, US

We investigate two issues in this paper. First, we examine the role of interface-traps on the device drain current in an SOI nanowire MOSFET. Afterwords, we investigate the role of the interface-roughness on the low-field [...]

Study of the RF Characteristics features of Optimized SOI – MESFETs

Tarik K., Vasileska D., Thornton T.J., Arizona State University, US

We have already demonstrated that the SOI MESFET device structure is a suitable candidate for micropower circuit applications due to its high anticipated cut-off frequency . Even though the device offers higher fT, there is [...]

Self-consistent Quantum Mechanical Treatment of the Ballistic Transport in 10 nm FinFET Devices Using CBR Method

Khan H., Mamaluy D., Vasileska D., Arizona State University, US

CBR technique has been used to perform fully quantum-mechanical simulation of 10nm FinFET devices with varying fin width. Device characteristics have been observed and compared to the experimental values. It is observed from the simulation [...]

Study of Cutoff Frequency Calculation in the Subthreshold Regime of Operation of the SOI – MESFETs

Tarik K., Vasileska D., Thornton T.J., Arizona State University, US

Micropower circuits based on sub-threshold MOSFETs are used in a variety of applications ranging from digital watches to medical implants. The principal advantage of a transistor operating in the sub-threshold regime is the minimum power [...]

Monte Carlo Transport Calculations of Strained SiGe Heterostructures from Ab-Initio Band-structures

Zorman B., Krishnan S., Vasileska D., Xu J., Van Schilfgaarde M., Arizona State University, US

The continued scaling of semiconductor devices creates numerous challenges which have to be overcome in order to achieve device behavior that satisfies speed and power constraints. Possible alternatives to conventional CMOS devices include strained-Si or [...]

Hole Transport Simulations in p-channel Si MOSFETs

Krishnan S., Vasileska D., Fischetti M.V., Arizona State University, US

We use a Monte Carlo method to investigate hole transport in ultrasmall p-channel MOSFETs with gate lengths of 25 nm. To model band-structure effects like warping, anisotropy and non-parabolicity on carrier transport, our device simulator [...]

Examination of the Effects of Unintentional Doping on the Operation of FinFETs with Monte Carlo Simulation Integrated with Fast Multipole Method (FMM)

Khan H., Ahmed S.S., Vasileska D., Arizona State University, US

Novel device structures such as dual gate SOI, Ultra thin body SOI, FinFETs, etc. have emerged as a solution to the ultimate scaling limits of conventional bulk MOSFETs. In this paper, we use a semi-classical [...]

Spin Polarization in GaAs/Al0.24Ga0.76As Heterostructures

Ashok A., Akis R., Vasileska D., Ferry D.K., Arizona State University, US

Spintronics is a new branch of electronics which involves the active control and manipulation of spin degrees of freedom in solid-state devices. Spin transport differs from charge transport as spin is a non-conserved quantity in [...]

Sub-Threshold Electron Mobility in SOI-MESFETs

Khan T., Vasileska D., Thornton T.J., Arizona State University, US

Micropower circuits use subthreshold MOSFETs that consume minimal power resulting from the combination of ultra-low drain currents (10-11 < Id < 10-5 A/µm) and small drain voltages required for saturation (Vd sat ~150-200mV). Unfortunately, sub-threshold [...]

Threshold Voltage Shifts in Narrow-Width SOI Devices Due to Quantum Mechanical Size-Quantization Effects

Ahmed S.S., Vasileska D., Arizona State University, US

We investigate the role of quantum-mechanical size-quantization effects in narrow-width SOI devices. In these structures, carriers experience a two dimensional confinement in a square quantum well at the semiconductor-oxide interface. This results not only in [...]