Puchner H. – TechConnect Briefs

Airgap and Line Slope Modeling for Interconnect

Badrieh F., Puchner H., Cypress Semiconductor, US

We have devised a generic methodology for characterizing airgaps and line slope and including those features in interconnect modeling. The method is silicon-based and can be used to accurately model the impact on capacitance. Our [...]

Simulation of Dynamic NBTI Degradation for a 90nm CMOS Technology

Wittmann R., Puchner H., Hinh L., Ceric H., Gehring A., Selberherr S., Vienna University of Technology, AT

The NBTI degradation was systematically investigated for a 90nm p-MOSFET by simulation and experiment. The reaction-diffusion model was extended for NBTI simulations at arbitrary gate voltage, frequency, and duty cycle within a calibrated range. Long-time [...]

Process and Device Calibration for 31/51nm NMOS/PMOS Devices fabricated by Direct Write E-Beam

Puchner H., Eib N., Kimball J., Mirabedini M., Haywood J., Aronowitz S., Cypress Semiconductor, US

In order to ensure predictability of process and device calibration tools, we manufactured CMOS devices with smallest end-of-line gate electrode dimensions of 31nm and 51nm by applying direct write e-beam lithography. A special test-chip was [...]

Nanoworld Semiconductor Industry – State and Future Challenges of Technology Computer Aided Design

Puchner H., Cypress Semiconductor, US

Several application examples of nanoscale techniques used to influence or enhance the understanding of material properties as well as processing behavior are presented. We will also present a review of first principle density functional theory [...]