Na M-H – TechConnect Briefs

RF Modeling of 45nm Low-Power CMOS Technology

Wang J., Li H., Pan L.H., Gogineni U., Groves R., Jagannathan B., Na M-H, Tonti W., Wachnik R., IBM Semiconductor Research and Development Center, US

As CMOS has grown to be one of the principle technologies for RF IC design, accurate modeling of MOSFETs at high frequencies becomes increasingly important. In this paper, we present an advanced RF modeling work [...]

SOI CMOS Compact Modeling based on TCAD Device Simulations

Botula A., Furkay S., Sheridan D.C., Johnson J.M., Na M-H, IBM Corporation, US

This work describes a TCAD-based methodology for generating compact models for circuit design in advance of hardware availability (predictive modeling). The exercise was performed on a 65nm node SOI CMOS technology. TCAD simulations accurate enough [...]

Predicting the SOI History Effect Using Compact Models

Na M-H, Watts J.S., Nowak E.J., Williams R.Q., Clark W.F., IBM Corporation, US

A simple and effective compact model methodology that predicts the history effect in silicon-on-insulator (SOI) is discussed. In this study we employ three physical parameters to modify the body-potentials of SOI FETs in an inverter [...]

A Compact Model Methodology for Device Design Uncertainty

Williams R., Watts J., Na M-H, Bernstein K., Internatoinal Business Machines Corporation, US

Todays ULSI chip and transistor technologies have a high degree of concurrency due to the complexity of new, advanced high performance features. This creates challenges for circuit designer who must account for the evolution of [...]