Ma G. – TechConnect Briefs

Improved Electric Field Decomposition Capacitance Model with 3-D Terminal and Fringe Components in Sub-28nm Interconnect

Zhang A., Li C., Liu J., He J., He X., He Y., Liu J., He J., He X., He Y., Ma G., Pan J., He J., He X., He Y., Hu G., Peking University Shenzhen Institute and PKU-HKUST Shenzhen-Hong Kong Institution, CN

In this paper, a parasitic capacitance model for a finite single three-dimensional (3-D) wire above an infinite plate in the nano-scale 3-D integrated circuit application is developed based on electric field decomposition (EFD). The capacitance [...]

Hot Carrier Effect and Oxide Reliability of T-FinFET Devices

He J., He X., He Y., Hu G., Li C., Liu J., He J., He X., He Y., Liu J., Ma G., He J., He X., He Y., Pan J., SoC Key Laboratory, Peking University Shenzhen Institute and PKU-HKUST Shenzhen-Hong Kong Institution, CN

Hot-carrier effect and oxide reliability of CMOS T-FinFET with 2.1nm-thick gate-SiO2 were investigated. It was found that hot-carrier immunity improves as the T-FinFET fin width (body thickness) decreases, which facilitates gate-length scaling, while it is [...]

An Effective Mobility Model for Tunneling Double-Gate MOSFET (T-FinFET)

He J., He X., Pan J., Liu J., Li C., Liu J., Hu G., Ma G., He J., He X., Chan M., SoC Key Laboratory, Peking University Shenzhen Institute and PKU-HKUST Shenzhen-Hong Kong Institution, CN

We have derived an analytical model for the effective field (Eeff) model of undoped Ultra-Thin Body (UTB) Double Gate (DG) SOI Tunneling MOSFETs ( T-FinFET) from the solution of the Poisson’s equation in this paper [...]