Ishimura K. – TechConnect Briefs

Compact Model HiSIM-DG both for Symmetrical and Asymmetrical DG-MOSFET Structures

Ishimura K., Sadachika N., Kusu S., Miura-Mattausch M., Hiroshima University, JP

In this work, the circuit simulation model for DG-MOSFET named HiSIM-DG, has been developed based on the complete surface-potential-based description. The model solves the Poisson equation to the vertical direction iteratively in quasi-2 dimensions including [...]

HiSIM-SOI: SOI-MOSFET Model for Circuit Simulation Valid also for Device Optimization

Sadachika N., Kusu S., Ishimura K., Murakami T., Kajiwara T., Hayashi T., Nishikawa Y., Yoshida T., Miura-Mattausch M., Hiroshima University, JP

SOI-MOSFETs are considered to be suitable for high performance as well as low power applications and its developments are tend to go toward the thinner SOI films to enhance the device characteristics. Thus compact models [...]

Modeling of Floating-Body Devices Based on Complete Potential Description

Sadachika N., Murakami T., Ando M., Ishimura K., Ohyama K., Miyake M., Mattausch H.J., Miura-Mattausch M., Miura-Mattausch M., Hiroshima University, JP

Advanced MOSFETs exploit the carrier confinement to suppress the short-channel effect, which is realized by reducing the bulk layer thickness. The ongoing developments of the multi-gate MOSFET as well as the fully-depleted SOI-MOSFET with ultra [...]