Forbes L. – TechConnect Briefs

Backside Nanoscale Texturing to Improve IR Response of Silicon Photodetectors

Forbes L., Louie M.Y., Oregon State University, US

When the silicon is not strongly absorbing in the near infrared a back side textured surface works in conjunction with a totally internally reflecting front side surface to best increase the absorption of near infrared [...]

Compact Model of Low – Frequency Noise in Nanoscale Metal-Oxide-Semiconductor Field Effect Transistors

Miller D.A., Jacob M.E., Forbes L., Oregon State University, US

At nanoscale device dimensions low frequency noise is dominated by one or more oxide traps capturing and emitting charge and generating large swings in the drain current or what is known as Random Telegraph Signal [...]

Atomistic Electrostatic Simulations Using Spice

Forbes L., Miller D.A., Jacob M.E., Oregon State University, US

The technique employed here to describe the three dimensional electrostatic field in a nano-scale CMOS n-channel FET near the threshold of conduction is using SPICE to solve the electrostatic equations. An atomistic solution will be [...]

Single Election Trapping in Nanoscale Transistors; RTS(Random Telegraph Signals) and l/f Noise

Forbes L., Miller D.A., Louie M.Y., Oregon State University, US

Random telegraph signal, RTS, noise[1] is most obvious in submicron devices with traps, for example in nanoscale MOS transistors, MOSFET’s, with a low number of carriers. RTS is sometimes an indicator of poor device quality [...]

1/f Noise and RTS(Random Telegraph Signal) Errors in Comparators and Sense Amplifiers

Forbes L., Miller D.A., Poocharoen P., Oregon State University, US

An analysis has previously been made of the increasing portion of the threshold voltage being occupied by thermal noise levels and the bit error rates in digital logic[1] and memory circuits [2-4]. This analysis has [...]

1/f Noise and RTS(Random Telegraph Signals) and Read Errors in Nanoscale Memories

Forbes L., Miller D.A., Louie M.Y., Oregon State University, US

The use of charge storage on nanoscale particles has been realized in silicon integrated circuit memories [1,2] and utilized in commercial products[2]. An analysis has previously been made of the increasing portion of the threshold [...]

Thermal Noise and Bit Error Rate Limits in Nanoscale Memories

Forbes L., Mudrow M., Wanalertlak W., Oregon State University, US

Analysis of the effects of thermal noise in nanoscale memories is presented. A theoretical analysis of thermal noise is used to predict the number of bit errors per year caused by thermal noise.

Technique for Time and Frequency Dependent Solutions of the Diffusion Equation: Application to temperature of nanoscale devices

Forbes L., Wanalertlak W., Louie M.Y., Oregon State University, US

Typical CMOS device currents have remained around 1mA/um while devices have scaled down. The projection into the 2010 time frame is 0.01um or 10nm dimensions with 0.5V power supplies which results for a minimum dimension [...]