An analysis has previously been made of the increasing portion of the threshold voltage being occupied by thermal noise levels and the bit error rates in digital logic and memory circuits [2-4]. This analysis has led to the prediction that there are fundamental limits imposed in digital circuits by thermal noise and that the scaling predicted by Moore’s law can not continue into the future. No consideration was, however, given to the errors that might be caused by l/f noise or random telegraph signals. In small transistors such as used in read sense amplifiers the l/f noise is caused by and can be characterized by random telegraph signals(RTS). These random signals can cause errors in the sense amplifiers and limit the ability to read the data stored in memories. In the case of RTS and l/f noise in the time domain representation the small but finite probability of an error will result from all traps happening to capture or emit electrons at the same time. If all traps in the sense amplifier transistor capture or emit electrons at the same time there will be an erroneous sense amplifier signal, the probability of such an error is small but it will occur at random times. This will result in an error or give the appearance of there being a “variable retention time” in a particular memory cell. The representation or modeling of the RTS or l/f noise of nanoscale devices that is easiest to understand is that done in the time domain. The capture and emission of a single electron in a nanoscale NMOS transistor of size W/L with be equivalent to a change in threshold voltage, VT, of ΔVT= q /(Cox W L) where q is the electronic charge, and Cox is the gate capacitance. The probability that there will be a coincidence of occurrence of a number of electrons contributing to a large change in threshold voltage and causing an error has been found to be described by a lognormal distribution. In a lognormal distribution the probability of a large value is of the order exp(-x). Published results show a 0.1% probability of a value twenty times the minimal RTS step of 10mV on a minimum size device in a 90nm technology with 9nm gate oxides. This would be 200mV, corresponding to fifty traps changing charge state. For a sense amplifier in 50nm technology with 2nm gate oxides and a transistor size of W/L = 2.5u/0.5u this translates into a large threshold voltage distribution if we assume the l/f noise varies according to the NLEV=0 SPICE model. If a DRAM sense amplifier is upset by a threshold voltage mismatch of ΔVT = 20mV then the calculated error rate could be as high as exp(-11). In reality there is not an error or variable retention time in the memory cell but rather a random and variable error occurring in the sense amplifier due to RTS or l/f noise which could happen nearly as often as every time a Gbit DRAM is read.  L.B. Kish, Physics Letters, A 305, pp. 144-149, 2002.  L. Forbes, M. Mudrow and W. Wanalertlak, IEE Electronics Letters, Vol. 42, No. 5, pp. 279-280, 2 March 2006.  M. Mudrow, W. Wanalertlak and L. Forbes, IEEE Workshop on Microelectronics and Electron Devices, Boise, 14 April 2006, pp. 39-40.  L. Forbes, M. Mudrow and W. Wanalertlak, NanoTech, Boston, 7-11 May 2006, Vol. 3, pp.78-81.  N. Tega, et. al, IEEE Int. Electron Device Meeting, San Francisco, Dec. 2006, paper 18.4.
Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2007 NSTI Nanotechnology Conference and Trade Show, Volume 1
Published: May 20, 2007
Pages: 197 - 200
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topics: Nanoelectronics, Photonic Materials & Devices