Choi C-H – TechConnect Briefs

Two-step approach for the nanofabrication of highly ordered ultra-long porous gold nanowires with an adjustable porosity for SERS-based sensors

Chauvin A., Delacôte C., Molina-Luna L., Boujtita M., Thiry D., Du K., Ding J., Choi C-H, Humbert B., Mevellec J.-Y., Tessier P.-Y., El Mel A.-A., Institut des matériaux Jean Rouxel, FR

Recently, nanoporous gold has been pointed out as a promising candidate for the development of SERS-based sensors for the detection of environmental toxins and small molecules [1]. One way to improve the detection ability of [...]

A Low-Voltage Droplet Manipulation via Tunable Wetting on a Polypyrrole (DBS) Surface

Xu W., Tian Y., Bisaria H., Ahn P., Li X., Tsai Y-T, Choi C-H, Yang E.H., Stevens Institute of Technology, US

Electrowetting on dielectric (EWOD) technique has been used to manipulate microliter-sized individual droplets for microfluidic application. However, EWOD-based techniques typically require relatively high actuation voltages (12-80V), which is undesirable for biomedical applications or the applications [...]

Droplet actuation in PPy redox process

Tsai Y-T, Choi C-H, Yang E.H., Stevens Institute of Technology, US

A wettability switchable surface will be demonstrated to study the contact angle hysteresis of liquid droplet. Manipulation of surface wettability can be applied in the field of biomedical (cell-surface interaction) and fluids dynamics (friction reduction). [...]

Implications of Gate Tunneling and Quantum Effects in the Gate-Channel Stack

Dutton R.W., Choi C-H, Stanford University, US

Simulation and modeling of gate tunneling current for thin-oxide MOSFETs and Double-Gate SOIs are discussed. Guidelines for design of leady MOS capacitors are proposed. Resonant gate tunneling current in DG SOI is simulated, based on [...]

Technology Limits and Compact Model for SiGe Scaled FETs

Dutton R.W., Choi C-H, Stanford, US

Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by 2/3 when the [...]

Mobility Extraction and Compact Modeling for FETs Using High-K Gate Materials

Dutton R.W., Liu Y., Choi C-H, Chen T.W., Stanford University, US

This simulation work discusses the impact of direct gate tunneling on effective mobility extraction methods, particularly the Inversion Charge Pumping (ICP) method proposed recently for transistors with high-k gate dielectrics. The valence-band electron gate tunneling [...]

Technology Limits and Compact Model for SiGe Scaled FETs

Dutton R.W., Choi C-H, Stanford, US

Stress relaxation in strained-Si MOSFETs can be significant in the presence of compressive stress imposed by trench isolation, especially for highly scaled active regions. Stress of the strained region is reduced by 2/3 when the [...]

Implications of Gate Tunneling and Quantum Effects in the Gate-Channel Stack

Dutton R., Choi C-H, Stanford University, US

Simulation and modeling of gate tunneling current for thin-oxide MOSFETs and Double-Gate SOIs are discussed. Guidelines for design of leady MOS capacitors are proposed. Resonant gate tunneling current in DG SOI is simulated, based on [...]