Cavelier M. – TechConnect Briefs

MOSFET Compact Modeling Issues for Low Temperature (77 K – 200 K) Operation

Martin P., Cavelier M., Fascio R., Ghibaudo G., CEA/LETI/MINATEC, FR

Advanced compact models are evaluated for simulation of mixed analog-digital circuits working at low temperature (77 to 200 K). This evaluation is performed on a dual gate oxide CMOS technology with 0.18 µm / 1.8 [...]

Explicit Short Channel Compact Model of Independent Double Gate Mosfet

Reyboz M., Rozeau O., Poiroux T., Martin P., Cavelier M., Jomaah J., CEA-LETI, FR

This paper describes an explicit short channel compact model of Independent Double Gate (IDG) MOSFET with undoped channel. The validity of this model is demonstrated by comparison with Atlas simulations. The model was implemented in [...]