Process Modeling – TechConnect Briefs

Papers:

Modeling of Deposition Process by Level Set Method

Jung H., Kwon O., Yoon S., Won T., Inha University, KR

In this paper, we report a novel method for effectively reducing the amount of calculation for a deposition rate at a specific level-set node. The proposed algorithm makes it possible to reduce the number of [...]

Layout Verification and Correction of CMOS-MEMS Layouts

Baidya B., He K., Mukherjee T., Carnegie Mellon, US

The advent of CMOS micromachining has introduced new design rules for fabrication of integrated CMOS-MEMS devices. This paper presents a context dependent DRC algorithm to handle the issues related to pre-fabrication verification of such layouts. [...]

Diffusion Induced Stresses in Microstructures of MEMS

Yang F., University of Rochester, US

The diffusion-induced stresses in silicon wafers were studied. The effect of local electric field on dopant diffusion was considered in the diffusion equation. Only one-dimension problem with a constant surface dopant concentration was investigated. The [...]

Semiempirical Direct Dynamics Trajectory Study of the Si+ (2P) + H2 -> SiH+ + H Reaction

Chaâbane N., Vach H., Peslherbe G.H., CNRS-Ecole Polytechnique, FR

Silicon chemical vapor deposition (CVD) is widely used in the microelectronic industry for the production of integrated circuits. For the underlying chemical reactions, the dynamical properties of the involved Si-H compounds are of fundamental interest. [...]

A Framework for Mask-Layout Synthesis Implementing a Level Set Method Simulator

Lee C.-Y., Antonsson E.K., California Institute of Technology, US

Recently, evolutionary methods have been developed to automate MEMS mask-layout synthesis [3]{[6]. These design synthesis methods are iterative searches in which each iteration consists of mask-layout modification, determination of etched shape via an arbitrary 3-D [...]

Bonding Pad Resistance. A Combined Approach

Bouche G., Gonella R., Sabouret E., Technology Modeling STMicroelectronics, FR

Introducing new intermetal materials, with improved electrical properties but lowered mechanical resistance, requires in terms of reliability to design new structures for pads. The test structures under fabrication have been simulated to try and evaluate [...]

Time Series Modelling of Surface Topography Generated by Ultrasonic Machining Process

Murti V.S.R., Naga Prasada Rao B., Krishna Reddy M., Osmania University, IN

In these studies the surface roughness profiles were modelled and analysed for a better understanding of the mechanism of metal erosion in USM. Different materials were selected for this purpose based on their diverse properties [...]

Journal: TechConnect Briefs
Volume: 1, Technical Proceedings of the 2001 International Conference on Modeling and Simulation of Microsystems
Published: March 19, 2001
Industry sector: Sensors, MEMS, Electronics
Topic: Modeling & Simulation of Microsystems
ISBN: 0-9708275-0-4