Patil G.C., Patil S.R., Patil G.C., Patil S.R., Borse H.S., Bhosale K.S., Jawake A.V., Aher S.R.
JSPM’s Rajarshi Shahu College of Engineering, IN
Keywords: double-gate, dual-K spacer, JLT
Recently, junctionless transistors (JLT) have attracted the attention of researchers due to simple fabrication flow and reduced short channel effects. Further, due to better gate control double gate JLT (DGJLT) seems to be a promising device for digital integrated circuits. Although in the literature it has been shown that, the addition of spacers reduces off-state leakage current(IOFF), the concept of dual-k spacer has not been studied in DGJLT. In this paper, for the first time a novel dual-k spacer double gate junctionless transistor (DK-DGJLT) has been proposed and the comparative analysis of DK-DGJLT and single-k spacer double gate junctionless (SK-DGJLT) has been carried out. The spacer material used in SK-DGJLT is silicon nitride (Si3N4) whereas spacer materials used in DK-DGJLT are Si3N4 and hafnium oxide. It has been found that, in comparison to SK-DGJLT, IOFF and the short channel effects mainly sub-threshold slope and drain induced barrier lowering in the case proposed DK-DGJLT are significantly low. Further, although the on-state drive current (ION) in proposed DK-DGJLT and SK-DGJLT is almost equal, ION/IOFF in the case of proposed DK-DGJLT is significantly high. This clearly shows that the proposed DK-DGJLT is the most promising device for low power digital integrated circuits.
Journal: TechConnect Briefs
Volume: 4, Advanced Manufacturing, Electronics and Microsystems: TechConnect Briefs 2015
Published: June 14, 2015
Pages: 218 - 221
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: Nanoelectronics
ISBN: 978-1-4987-4730-1