Papers – Page 19 – TechConnect Briefs

Multiscale Modeling of Stress-Mediated Diffusion in Silicon, Ab Initio to Continuum

Windl W., Laudon M., Daw M.S., Carlson N.N., Masquelier M.P., Motorola, Inc., US

The introduction of new ‘back end’ materials, as well as the further scaling of silicon device dimensions, has raised the level of stress in dvice structures. Current engineering simulations of diffusion neglect the direct effect [...]

Ultrasmall Devices: Are We Ready for Quantum Effects?

Ferry D.K., Arizona State University, US

It is clear that continued scaling of semiconductor devices will bring us to a regime with gate lengths of less than 70 nm within another decade. While there are questions to be answered in the [...]

Top Down Design of MEMS

Fedder G.K., Carnegie Mellon University, US

A top-down design flow for suspended MEMS is described, starting with schematic capture of a design topology, followed by behavioral simulation, layout generation, parasitic extraction, and final verification. Support for this flow requires a MEMS [...]

Automatic Device Design Optimization with TCAD Frameworks

Stockinger M., Selberherr S., Technical University of Vienna, AT

A design optimization method is presented which utilizes automatic optimization capabilities within TCAD frameworks. This method is applied to doping profile optimizations of ultra-low-power CMOS transistors with 0.25 and 0.1 um gate lengths. Two different [...]