In recent years, printed electronics starts to evolve from single components to systems where interconnects are essential for transistors to be connected into circuits. For complicated electronic circuits systems such as integrated circuit (IC), multilevel interconnects are needed to avoid excessive cross-over of interconnect tracks. Conventionally, multilevel interconnects are realized by repeated deposition of insulating layers and lithographic patterning of via holes. In the present work, two printed via processes are reported for interconnecting transistors and circuits through dielectric layers. The first process relies on printing Ag paste on SiNx layer then annealing at high temperature to destroy the insulation of SiNx . The second process involves printing alkali such as NaOH, KOH and TMAH to an aluminum oxide dielectric layer in-situ etch. Both processes can establish via holes to facilitate electric connection through dielectric layer. The above processes have been applied to fabrication IZO transistors. The fabrication process consists of the following steps: first, ITO ink is printed on glass substrate to form the gate electrodes. Then, aluminum oxide dielectric layer covering the whole substrate is deposited using ALD. Following the deposition of dielectric layer, via holes are fabricated by printing NaOH etchant, which provides the conductive tunnel from the ITO gate electrode to the upper surface of dielectric layer. Then, IZO semiconductor channels and ITO source/drain electrodes are printed on the dielectric layer to construct the transistors. The printed transistors exhibited mobility of more than 5cm2/Vs and on/off ratio of 106. The whole fabrication process involves only printing and film deposition, excluding any photolithographic patterning. The technology is also applied to print transistors on silicon substrate with SiO2 as the dielectric layer, the field effect saturation mobility was ca. 1.2 cm2/Vs and on/off ratio reached to 106. An inverter circuit was constructed by connecting two transistors through the printed via technique. The inverter exhibited good logic function with a maximum voltage gain of 14. As both the electrode material (ITO) and semiconductor material (IZO) are transparent, the printed circuit array on a glass substrate is also transparent. In this study, two printed via processes have been developed for interconnecting transistors and circuits through dielectric layers. High mobility and high voltage gains were exhibited with the printed transistors and inverters, demonstrating the feasibility of printed via process. The method is scalable to large array of complicated circuits, paving the way to construct integrated circuits by printing method.
Journal: TechConnect Briefs
Volume: 4, Advanced Manufacturing, Electronics and Microsystems: TechConnect Briefs 2016
Published: May 22, 2016
Pages: 155 - 159
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: Inkjet Design, Materials & Fabrication