Chen Q., Goo J-S, Subba N., Cai X., An J.X., Ly T., Wu Z-Y, Suryagandh S., Thuruthiyil C., Radwin M., Zamudio L., Yonemura J., Assad F., Pelella M.M., Icel A.B.
Advanced Micro Devices, US
Keywords: compact modeling, hysteresis, SOI
Exploiting the asymmetric nature of interactions among hysteresis, “nonFET”, and DC characteristics, an a priori hysteresis modeling methodology has been proposed as an essential part of an improved model extraction flow for advanced PD SOI technologies. It has been successfully implemented on a state-of-the-art 90 nm technology demonstrating projected benefits, including minimum deviation of nonFET characteristics from hardware data, improved model extraction efficiency, improved model accuracy for hysteresis over a wide range of Vdd/T, and efficient implementation of automatic hysteresis optimization.
Journal: TechConnect Briefs
Volume: Technical Proceedings of the 2005 Workshop on Compact Modeling
Published: May 8, 2005
Pages: 159 - 162
Industry sectors: Advanced Materials & Manufacturing | Sensors, MEMS, Electronics
Topic: Nanoparticle Synthesis & Applications
ISBN: 0-9767985-3-0