LDMOS – Page 2 – TechConnect Briefs

High Voltage MOSFET’s Modeling Review

Ma Y., Jeng M-C, Liu Z., Cadence Design System, Inc., US

In this paper, different modeling solutions for HVMOS and LDMOS are discussed, current status of compact model development for HVMOS/LDMOS are reviewed. Macro models are widely used to model HVMOS and LDMOS devices. Different macro [...]

Compact Capacitance Model of LDMOS for Circuit Simulation

Ma J., Ma Y., Chen P., Liang H., Ma J., Ma Y., Jeng M-C, Liu Z., Cadence Design Systems, Inc., US

Capacitance modeling in LDMOS is much more complicated than that in bulk MOSFET’s due to the fact of non-uniform lateral channel doping, the extended gate drain overlap region and its interaction with channel charges. Measurements [...]

High-Voltage LDMOS Compact Modeling

Willemsen M.B., van Langevelde R., Klaassen D.B.M., Philips Research, NL

In compact modeling of high-voltage LDMOS devices often a sub-circuit approach is used. While for the channel region a standard compact MOS model (for example BSIM4, MM11 or PSP) is used, the drift region is [...]

Compact Modelling of High-Voltage LDMOS Devices

Aarts A.C.T., van der Hout R., van Langevelde R., van der Hout R., van Langevelde R., Scholten A.J., Willemsen M.B., Klaassen D.B.M., Philips Research Laboratories, NE

In this paper various modelling approaches for Laterally Double-Di used MOS (LDMOS) devices are discussed. Characterisation results for the new compact LDMOS model called MOS Model 20 are presented. Measurements of the dc-current, its conductances [...]