FPGA – TechConnect Briefs

Hybrid CMOS/nanodevice circuits with tightly integrated memory and logic functionality

Strukov D.B., University of California at Santa Barbara, US

We propose dynamic CMOL FPGA circuits which have potentials to perform massively parallel high throughput computations and in particular suitable for pattern matching tasks. The main difference of the proposed circuits from previously suggested hybrid [...]

An FPGA Architecture Using Vertical Silicon Nanowire Transistors

Bindal A., Wickramaratne D., Hamedi-Hagh S., San Jose State University, US

This study presents an FPGA architecture using vertical silicon nanowire transistors. A complete picture from designing ultra low-power silicon nanowire transistors to their use in an FPGA architecture is given. Post-layout, worst-case rise delay changes [...]

An All-Digital Cantilever Controller for MRFM and Scanned Probe Microscopy using a Combined DSP/FPGA Design

de Roover D., Porter II L.M., Emami-Naeini A., Marohn J.A., Kuehn S., Garner S., Smith D.D., SC Solutions, Inc., US

An all-digital cantilever controller for magnetic resonance force microscopy (MRFM) was developed through a close collaboration between SC Solutions, Cornell University, and the U.S. Army Research Laboratory. The advantage of an all-digital controller is its [...]

Hardware Implementation of Programmable Neural Networks for CHEMFET Signals Analysis in SEWING Project

Klepaczko A., Napieralski A., Kielbik R., Moreno J.M., Technical University of Lodz, PL

This paper focuses on problems of hardware implementation of neural networks (NN) in the re-programmable structures. New class of these devices, which integrate in one silicon wafer entire microprocessor systems (Systems-on-Chip), facilitates NN construction and [...]