Hybrid CMOS/nanodevice circuits with tightly integrated memory and logic functionality


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We propose dynamic CMOL FPGA circuits which have potentials to perform massively parallel high throughput computations and in particular suitable for pattern matching tasks. The main difference of the proposed circuits from previously suggested hybrid circuits is that nanodevice utilization can be as high as 25% (compared to ~0.1% of original ones) enabling much more efficient use of nanosubsystem. For example, our estimates show that dynamic CMOL FPGA circuits based on 130-nm CMOS technology and one crossbar layer with 20-nm nanowire half pitch enable throughput over 10^19 bits/s/cm2 for matching of 10^7 1000-wide patterns assuming practical power consumption density and lack of any optimization. More generally, we argue that the proposed concept could be viewed as the first tight symbiotic integration of memory and logic functions for high performance computing and can be implemented with variety of 3D integration schemes and memory technologies.

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Journal: TechConnect Briefs
Volume: 2, Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational
Published: June 13, 2011
Pages: 9 - 12
Industry sector: Sensors, MEMS, Electronics
Topics: Nanoelectronics, Photonic Materials & Devices
ISBN: 978-1-4398-7139-3