Tavernier C. – TechConnect Briefs

Advanced physics for simulation of ultrascaled devices with UTOXPP Solver

Garetto D., Rideau D., Tavernier C., Leblebiciand Y., Schmid A., Jaouen H., IBM corp., FR

As the conventional scaling down of MOSFET dimensions faces physical and economical limits, the performances of novel solutions such as high-K dielectrics, mechanical strain and substrate orientation or alternative device structures, such as fully-depleted SOI [...]

Modeling study of capacitance and gate current in strained High–K Metal gate technology: impact of Si/SiO2/HK interfacial layer and band structure model

Garetto D., Rideau D., Dornel E., Clark W.F., Tavernier C., Leblebici Y., Schmid A., Jaouen H., IBM France, FR

The importance of developing predictive modeling tools has considerably increased with the diffusion of nanoscale technologies, in which strained layers and heterojunctions determine the materials modeling complexity. A self--consistent Poisson--Schroedinger solver based on a full-band [...]

Dynamic Charge Sharing modeling for surface potential based models

Quenette V., Rideau D., Clerc R., Tavernier C., Jaouen H., ST Microelectronics, FR

Technology tuning by design means have been recently pointed out. Particularly, the possibility of back bias polarization (VB) to tune the threshold voltage (VT) has been commonly adopted in advanced devices. As a consequence the [...]

Embedded non–volatile memory study with surface potential based model

Garetto D., Zaka A., Quenette V., Rideau D., Dornel E., Clark W.F., Minondo M., Tavernier C., Rafhay Q., Clerc R., Schmid A., Leblebici Y., Jaouen H., STMicroelectronics, FR

Coupling coefficients calculation is known to be a critical issue in Non-Volatile Memory cell compact modelling. To this purpose, the accuracy of the capacitive network method can be significantly improved using the charge balance method, [...]