Patil S.R. – TechConnect Briefs

Impact of High-k gate oxide on intrinsic device Performance of Junctionless Transistor (JLT)

Borse H.S., Jawake A.V., Aher S.R., Bhosale K.S., Patil G.C., Patil S.R., Patil G.C., Patil S.R., Bormane D.S., JSPM’s Rajarshi Shahu College of Engineering, IN

Junctionless transistor (JLT) attracts the researchers due to its advantages over conventional MOSFET’s namely high scalability, simple process flow, and low thermal budget. However, scaling of JLT below 20 nm regime results increase in off [...]

A Novel Dual-K Spacer Double Gate Junctionless Transistor for Digital Integrated Circuits

Patil G.C., Patil S.R., Patil G.C., Patil S.R., Borse H.S., Bhosale K.S., Jawake A.V., Aher S.R., JSPM’s Rajarshi Shahu College of Engineering, IN

Recently, junctionless transistors (JLT) have attracted the attention of researchers due to simple fabrication flow and reduced short channel effects. Further, due to better gate control double gate JLT (DGJLT) seems to be a promising [...]

A Novel GaAs-on-Si MOSFET for Analog Integrated Circuits

Jawake A.V., Aher S.R., Borse H.S., Bhosale K.S., Patil G.C., Patil S.R., Patil G.C., Patil S.R., JSPM’s Rajarshi Shahu College of Engineering, IN

Over the last few decades silicon has proven its superiority in the semiconductor world with respect to properties like small mass, good carrier capability, low cost, maximum wafer diameter etc. However, since on-state drive current [...]

Impact of Gate Oxide Thickness and Channel Thickness on DC Performance of Carbon Nanotube Tunnel FET

Bhosale K.S., Jawake A.V., Aher S.R., Borse H.S., Patil G.C., Patil S.R., Patil G.C., Patil S.R., JSPM’s Rajarshi Shahu College of Engineering, IN

The scaling down of conventional complementary metal–oxide–semiconductor technology is suffering from fundamental limitations. To overcome these problems, novel engineering solutions like improving the device architecture,introducing materials into the channel region with superior transport properties, and [...]