Murakami T. – TechConnect Briefs

HiSIM-SOI: SOI-MOSFET Model for Circuit Simulation Valid also for Device Optimization

Sadachika N., Kusu S., Ishimura K., Murakami T., Kajiwara T., Hayashi T., Nishikawa Y., Yoshida T., Miura-Mattausch M., Hiroshima University, JP

SOI-MOSFETs are considered to be suitable for high performance as well as low power applications and its developments are tend to go toward the thinner SOI films to enhance the device characteristics. Thus compact models [...]

Modeling of Floating-Body Devices Based on Complete Potential Description

Sadachika N., Murakami T., Ando M., Ishimura K., Ohyama K., Miyake M., Mattausch H.J., Miura-Mattausch M., Miura-Mattausch M., Hiroshima University, JP

Advanced MOSFETs exploit the carrier confinement to suppress the short-channel effect, which is realized by reducing the bulk layer thickness. The ongoing developments of the multi-gate MOSFET as well as the fully-depleted SOI-MOSFET with ultra [...]

Kinetic Monte Carolo Simulation of Thin Film Growth with Void Formation – Application to via Filling

Hiwatari Y., Kaneko Y., Ohara K., Murakami T., Kanazawa University, JP

In this paper, we study the void formation during via ﬁlling as a model of copper damascene plating for LSI interconnects. We developed a new model for crystal growth which enables us to study the [...]

Kinetic Monte Carolo Simulation of Thin Film Growth with Void Formation – Application to via Filling

Hiwatari Y., Kaneko Y., Ohara K., Murakami T., Kanazawa University, JP

In this paper, we study the void formation during via ﬁlling as a model of copper damascene plating for LSI interconnects. We developed a new model for crystal growth which enables us to study the [...]