Modeling of Direct Tunneling Current in Multi-Layer Gate Stacks
Dunga M.V., Xi X., He J., Polishchuk I., Lu Q., Chan M., Niknejad A., Hu C., University of California-Berkeley, US
Device scaling to improve performance calls for reduction of the gate oxide thickness but at a cost of increased direct tunneling gate current. The ITRS 2001 recognizes the need of gate scaling below 2nm and [...]